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[/] [ddr2_sdram/] [trunk/] [ipcore_dir/] [DDR2_Ram_Core/] [user_design/] [par/] [UB_DDR2_64bit_UCF.ucf] - Rev 2
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########################################## File : UB_DDR2_64bit_UCF.ucf# Autor : UB## Constraint-File fuer das externe DDR2-SDRAM# auf dem Spartan-3A Board (MT47H32M16xx-3)## Size = 64MByte#################################################################################### Port-Zuweisungen########################################### ----------------------------------------------------# -- DDR2 SDRAM-Port-Pins# ----------------------------------------------------# cntrl0_ddr2_a : out std_logic_vector(12 downto 0) := (others => '0');# cntrl0_ddr2_ba : out std_logic_vector(1 downto 0) := (others => '0');# cntrl0_ddr2_ck : out std_logic_vector(0 downto 0) := (others => '0');# cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0) := (others => '0');# cntrl0_ddr2_cke : out std_logic := '0';# cntrl0_ddr2_cs_n : out std_logic := '0';# cntrl0_ddr2_ras_n : out std_logic := '0';# cntrl0_ddr2_cas_n : out std_logic := '0';# cntrl0_ddr2_we_n : out std_logic := '0';# cntrl0_ddr2_odt : out std_logic := '0';# cntrl0_ddr2_dm : out std_logic_vector(1 downto 0) := (others => '0');# cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0');# cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0) := (others => '0');# cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0) := (others => '0');# cntrl0_rst_dqs_div_in : in std_logic;# cntrl0_rst_dqs_div_out : out std_logic# ----------------------------------------------------################################################################################################################################################################# Clock constraints#####################################################################################################################NET "INST_DDR2_RAM_CORE/infrastructure_top0/sys_clk_ibuf" TNM_NET = "SYS_CLK";TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 7.5187 ns HIGH 50 %;######################################################################################################################### Calibration Circuit Constraints######################################################################################################################### Placement constraints for LUTS in tap delay ckt#######################################################################################################################INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l1" RLOC=X0Y6;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l1" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l2" RLOC=X0Y7;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l2" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l3" RLOC=X0Y7;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l3" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l4" RLOC=X1Y6;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l4" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l5" RLOC=X1Y6;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l5" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l6" RLOC=X1Y7;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l6" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l7" RLOC=X1Y7;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l7" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l8" RLOC=X0Y4;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l8" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l9" RLOC=X0Y4;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l9" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l10" RLOC=X0Y5;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l10" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l11" RLOC=X0Y5;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l11" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l12" RLOC=X1Y4;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l12" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l13" RLOC=X1Y4;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l13" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l14" RLOC=X1Y5;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l14" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l15" RLOC=X1Y5;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l15" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l16" RLOC=X0Y2;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l16" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l17" RLOC=X0Y2;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l17" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l18" RLOC=X0Y3;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l18" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l19" RLOC=X0Y3;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l19" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l20" RLOC=X1Y2;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l20" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l21" RLOC=X1Y2;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l21" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l22" RLOC=X1Y3;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l22" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l23" RLOC=X1Y3;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l23" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l24" RLOC=X0Y0;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l24" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l25" RLOC=X0Y0;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l25" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l26" RLOC=X0Y1;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l26" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l27" RLOC=X0Y1;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l27" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l28" RLOC=X1Y0;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l28" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l29" RLOC=X1Y0;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l29" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l30" RLOC=X1Y1;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l30" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l31" RLOC=X1Y1;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l31" U_SET = delay_calibration_chain;######################################################################################################################## Placement constraints for first stage flops in tap delay ckt ########################################################################################################################INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" RLOC=X0Y6;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" RLOC=X0Y6;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" RLOC=X0Y7;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" RLOC=X0Y7;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" RLOC=X1Y6;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" RLOC=X1Y6;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" RLOC=X1Y7;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" RLOC=X1Y7;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" RLOC=X0Y4;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" RLOC=X0Y4;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" RLOC=X0Y5;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" RLOC=X0Y5;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" RLOC=X1Y4;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" RLOC=X1Y4;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" RLOC=X1Y5;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" RLOC=X1Y5;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" RLOC=X0Y2;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" RLOC=X0Y2;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" RLOC=X0Y3;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" RLOC=X0Y3;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" RLOC=X1Y2;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" RLOC=X1Y2;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" RLOC=X1Y3;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" RLOC=X1Y3;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" RLOC=X0Y0;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" RLOC=X0Y0;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" RLOC=X0Y1;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" RLOC=X0Y1;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" RLOC=X1Y0;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" RLOC=X1Y0;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" RLOC=X1Y1;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" U_SET = delay_calibration_chain;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" RLOC=X1Y1;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" U_SET = delay_calibration_chain;######################################################################################################################### BEL constraints for LUTS in tap delay ckt#######################################################################################################################INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l0" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l1" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l2" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l3" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l4" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l5" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l6" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l7" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l8" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l9" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;################################################################################################################ Area Group Constraint For tap_dly and cal_ctl module.##############################################################################################################INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l0" RLOC_ORIGIN=X28Y16;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/cal_ctl0/*" AREA_GROUP = cal_ctl;INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/*" AREA_GROUP = cal_ctl;AREA_GROUP "cal_ctl" RANGE = SLICE_X26Y8:SLICE_X37Y21;AREA_GROUP "cal_ctl" GROUP = CLOSED;#################################################################################################################**************************************************************************************************************## CONTROLLER 0 ##**************************************************************************************************************################################################################################################################## I/O STANDARDS#################################################################################################################NET "sys_clk_in" IOSTANDARD = LVCMOS33;NET "cntrl0_ddr2_a[*]" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_ba[*]" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_I;NET "cntrl0_ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_I;NET "cntrl0_ddr2_cke" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_cs_n" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_ras_n" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_cas_n" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_we_n" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_odt" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_dm[*]" IOSTANDARD = SSTL18_I;NET "cntrl0_rst_dqs_div_in" IOSTANDARD = SSTL18_I;NET "cntrl0_rst_dqs_div_out" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_dq[*]" IOSTANDARD = SSTL18_I;NET "cntrl0_ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_I;NET "cntrl0_ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_I;##################################################################################################################### Banks 2# Pin Location Constraints for System clock signals#####################################################################################################################NET "sys_clk_in" LOC = "V12"; # on board clock#NET "sys_clk_in" LOC = "U12"; #external clock##################################################################################################################### Banks 3# Pin Location Constraints for Clock,Masks, Address, and Controls####################################################################################################################NET "cntrl0_ddr2_ck[0]" LOC = "M1" ;NET "cntrl0_ddr2_ck_n[0]" LOC = "M2" ;NET "cntrl0_ddr2_dm[0]" LOC = "J3" ;NET "cntrl0_ddr2_dm[1]" LOC = "E3" ;NET "cntrl0_ddr2_a[0]" LOC = "R2" ;NET "cntrl0_ddr2_a[1]" LOC = "T4" ;NET "cntrl0_ddr2_a[2]" LOC = "R1" ;NET "cntrl0_ddr2_a[3]" LOC = "U3" ;NET "cntrl0_ddr2_a[4]" LOC = "U2" ;NET "cntrl0_ddr2_a[5]" LOC = "U4" ;NET "cntrl0_ddr2_a[6]" LOC = "U1" ;NET "cntrl0_ddr2_a[7]" LOC = "Y1" ;NET "cntrl0_ddr2_a[8]" LOC = "W1" ;NET "cntrl0_ddr2_a[9]" LOC = "W2" ;NET "cntrl0_ddr2_a[10]" LOC = "T3" ;NET "cntrl0_ddr2_a[11]" LOC = "V1" ;NET "cntrl0_ddr2_a[12]" LOC = "Y2" ;NET "cntrl0_ddr2_ba[0]" LOC = "P3" ;NET "cntrl0_ddr2_ba[1]" LOC = "R3" ;NET "cntrl0_ddr2_cke" LOC = "N3" ;NET "cntrl0_ddr2_cs_n" LOC = "M5" ;NET "cntrl0_ddr2_ras_n" LOC = "M3" ;NET "cntrl0_ddr2_cas_n" LOC = "M4" ;NET "cntrl0_ddr2_we_n" LOC = "N4" ;NET "cntrl0_ddr2_odt" LOC = "P1" ;#NET "reset_in_n" LOC = "T15" | IOSTANDARD = LVTTL | PULLDOWN ;#NET "cntrl0_led_error_output1" LOC = "R20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = QUIETIO | PULLDOWN ;#NET "cntrl0_data_valid_out" LOC = "T19" | IOSTANDARD = LVTTL;#NET "cntrl0_init_done" LOC = "V16" | IOSTANDARD = LVTTL;################################################################################################################ MAXDELAY constraints############################################################################################################################################################################################################################## Constraint to have the tap delay inverter connection wire length to be the same and minimum to get## accurate calibration of tap delays. The following constraints are independent of frequency.##############################################################################################################NET "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/tap[7]" MAXDELAY = 400ps;NET "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/tap[15]" MAXDELAY = 400ps;NET "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/tap[23]" MAXDELAY = 400ps;################################################################################################################ MAXDELAY constraint on inter LUT delay elements. This constraint is required to minimize the## wire delays between the LUTs.##############################################################################################################NET "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay*dqs_delay_col*/delay*" MAXDELAY = 190 ps;NET "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/delay*" MAXDELAY = 200 ps;################################################################################################################ Constraint from the dqs PAD to input of LUT delay element.##############################################################################################################NET "INST_DDR2_RAM_CORE/top_00/dqs_int_delay_in*" MAXDELAY = 580 ps;################################################################################################################ Constraint from rst_dqs_div_in PAD to input of LUT delay element.##############################################################################################################NET "INST_DDR2_RAM_CORE/top_00/dqs_div_rst" MAXDELAY = 460 ps;################################################################################################################ Following are the MAXDELAY constraints on delayed rst_dqs_div net and fifo write enable signals.## These constraints are required since these paths are not covered by timing analysis. The requirement is total## delay on delayed rst_dqs_div and fifo_wr_en nets should not exceed the clock period.##############################################################################################################NET "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div" MAXDELAY = 3007 ps;NET "INST_DDR2_RAM_CORE/top_00/data_path0/fifo*_wr_en*" MAXDELAY = 3007 ps;################################################################################################################ The MAXDELAY value on fifo write address should be less than clock period. This constraint is## required since this path is not covered by timing analysis.##############################################################################################################NET "INST_DDR2_RAM_CORE/top_00/data_path0/fifo*_wr_addr*" MAXDELAY = 6390 ps;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 1, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[1]" LOC = K5;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1" LOC = SLICE_X0Y58;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1" LOC = SLICE_X0Y59;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 0, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[0]" LOC = H1;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0" LOC = SLICE_X2Y62;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0" LOC = SLICE_X2Y63;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 3, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[3]" LOC = L3;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3" LOC = SLICE_X2Y52;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3" LOC = SLICE_X2Y53;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 2, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[2]" LOC = K1;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2" LOC = SLICE_X0Y50;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2" LOC = SLICE_X0Y51;################################################################################################################ constraints for bit cntrl0_ddr2_dqs, 0, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dqs[0]" LOC = K3;################################################################################################################ constraints for bit cntrl0_ddr2_dqs_n, 0, location in tile: 0###########################################################################################################################################################################NET "cntrl0_ddr2_dqs_n[0]" LOC = K2;################################################################################################################ LUT location constraints for dqs_delayed_col0##############################################################################################################INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" LOC = SLICE_X2Y55;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" LOC = SLICE_X2Y55;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" LOC = SLICE_X2Y54;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" LOC = SLICE_X2Y54;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" LOC = SLICE_X3Y55;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" LOC = SLICE_X3Y54;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" BEL = G;################################################################################################################ LUT location constraints for dqs_delayed_col1##############################################################################################################INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" LOC = SLICE_X0Y55;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" LOC = SLICE_X0Y55;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" LOC = SLICE_X0Y54;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" LOC = SLICE_X0Y54;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" LOC = SLICE_X1Y55;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" LOC = SLICE_X1Y54;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" BEL = G;################################################################################################################ Slice location constraints for Fifo write address and write enable##############################################################################################################INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y50;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y50;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y49;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y49;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y49;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y49;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y50;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y50;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst/delay_ff" LOC = SLICE_X1Y53;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst/delay_ff_1" LOC = SLICE_X3Y53;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 5, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[5]" LOC = L1;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5" LOC = SLICE_X2Y50;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5" LOC = SLICE_X2Y51;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 4, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[4]" LOC = L5;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4" LOC = SLICE_X0Y52;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4" LOC = SLICE_X0Y53;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 7, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[7]" LOC = H2;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7" LOC = SLICE_X0Y62;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7" LOC = SLICE_X0Y63;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 6, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[6]" LOC = K4;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6" LOC = SLICE_X2Y58;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6" LOC = SLICE_X2Y59;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 9, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[9]" LOC = G4;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1" LOC = SLICE_X2Y78;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1" LOC = SLICE_X2Y79;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 8, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[8]" LOC = F2;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0" LOC = SLICE_X0Y70;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0" LOC = SLICE_X0Y71;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 11, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[11]" LOC = H6;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3" LOC = SLICE_X2Y76;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3" LOC = SLICE_X2Y77;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 10, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[10]" LOC = G1;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2" LOC = SLICE_X2Y68;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2" LOC = SLICE_X2Y69;################################################################################################################ constraints for bit cntrl0_ddr2_dqs, 1, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dqs[1]" LOC = K6;################################################################################################################ constraints for bit cntrl0_ddr2_dqs_n, 1, location in tile: 0###########################################################################################################################################################################NET "cntrl0_ddr2_dqs_n[1]" LOC = J5;################################################################################################################ LUT location constraints for dqs_delayed_col0##############################################################################################################INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" LOC = SLICE_X2Y75;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" LOC = SLICE_X2Y75;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" LOC = SLICE_X2Y74;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" LOC = SLICE_X2Y74;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" LOC = SLICE_X3Y75;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" LOC = SLICE_X3Y74;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" BEL = G;################################################################################################################ LUT location constraints for dqs_delayed_col1##############################################################################################################INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" LOC = SLICE_X0Y75;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" LOC = SLICE_X0Y75;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" LOC = SLICE_X0Y74;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" LOC = SLICE_X0Y74;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" LOC = SLICE_X1Y75;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" LOC = SLICE_X1Y74;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" BEL = G;################################################################################################################ Slice location constraints for Fifo write address and write enable##############################################################################################################INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y69;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y69;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y70;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y70;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y69;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y69;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y70;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y70;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst/delay_ff" LOC = SLICE_X1Y72;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst/delay_ff_1" LOC = SLICE_X3Y72;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 13, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[13]" LOC = F1;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5" LOC = SLICE_X2Y70;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5" LOC = SLICE_X2Y71;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 12, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[12]" LOC = H5;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4" LOC = SLICE_X0Y76;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4" LOC = SLICE_X0Y77;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 15, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[15]" LOC = F3;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7" LOC = SLICE_X0Y78;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7" LOC = SLICE_X0Y79;################################################################################################################ constraints for bit cntrl0_ddr2_dq, 14, location in tile: 0##############################################################################################################NET "cntrl0_ddr2_dq[14]" LOC = G3;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6" LOC = SLICE_X0Y68;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6" LOC = SLICE_X0Y69;################################################################################################################ constraints for bit cntrl0_rst_dqs_div_in, 1, location in tile: 1##############################################################################################################NET "cntrl0_rst_dqs_div_in" LOC = H4;################################################################################################################ Slice location constraints for delayed rst_dqs_div signal##############################################################################################################INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one" LOC = SLICE_X0Y67;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two" LOC = SLICE_X0Y66;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three" LOC = SLICE_X0Y67;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four" LOC = SLICE_X1Y66;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four" BEL = F;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five" LOC = SLICE_X1Y66;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five" BEL = G;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six" LOC = SLICE_X1Y67;INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six" BEL = G;################################################################################################################ constraints for bit cntrl0_rst_dqs_div_out, 1, location in tile: 0##############################################################################################################NET "cntrl0_rst_dqs_div_out" LOC = H3;#################################################################################INST "INST_DDR2_RAM_CORE/top_00/controller0/rst_dqs_div_r" LOC = SLICE_X4Y66;