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https://opencores.org/ocsvn/ddr2_sdram/ddr2_sdram/trunk
Subversion Repositories ddr2_sdram
[/] [ddr2_sdram/] [trunk/] [iseconfig/] [Prj_12_DDR2.projectmgr] - Rev 2
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<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="Prj_12_DDR2" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top</ClosedNode>
<ClosedNode>/Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top/infrastructure_top0 - DDR2_Ram_Core_infrastructure_top - arc</ClosedNode>
<ClosedNode>/Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top/top_00 - DDR2_Ram_Core_top_0 - arc</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Prj_12_DDR2</SelectedItem>
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<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>Prj_12_DDR2</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
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<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
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<SelectedItem></SelectedItem>
</SelectedItems>
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<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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<CurrentItem></CurrentItem>
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<ItemView guiview="File" >
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Buttons_VHDL.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
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<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>work</ClosedNode>
</ClosedNodes>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
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<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
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<CurrentItem></CurrentItem>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
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<SelectedItem>Edit Constraints (Text)</SelectedItem>
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<CurrentItem>Edit Constraints (Text)</CurrentItem>
</ItemView>
</Project>