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[/] [ddr3_sdram/] [trunk/] [system.ucf] - Rev 3
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# For SiOI FS6484 Spartan 6 board
# Copyright 2012 SiOI
CONFIG VCCAUX=3.3;
Net mck62M5 TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 16.000 ns HIGH 50% INPUT_JITTER 100.0ps;
Net mck62M5 LOC=M3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50;
Net mled<0> LOC=AB2 | IOSTANDARD=LVCMOS33 | SLEW=QUIETIO;
Net mled<1> LOC=AA2 | IOSTANDARD=LVCMOS33 | SLEW=QUIETIO;
Net mbtn<0> LOC=Y3 | IOSTANDARD=LVCMOS33 | PULLUP;
Net mbtn<1> LOC=AB3 | IOSTANDARD=LVCMOS33 | PULLUP;
Net txd LOC=B10 | IOSTANDARD=LVCMOS33;
Net rxd LOC=A10 | IOSTANDARD=LVCMOS33;
#Net sda LOC=P2 | IOSTANDARD=SSTL15_II;
#Net scl LOC=L4 | IOSTANDARD=SSTL15_II;
# PAR usually gets the following right but use manual placement if it fails:
#INST "*BUFPLLS[0].bufpll_625_18" LOC=BUFPLL_X0Y3;
#INST "*BUFPLLS[1].bufpll_625_18" LOC=BUFPLL_X2Y3;
# Ignore the timing of the GPIO outputs from the MicroBlaze:
inst "mcs_0/U0/iomodule_0/IOModule_Core_I1/GPO_I?/gpo_io_i_?" TIG;
# Apply TIGs to reset circuitry, allowing it to take multiple clock cycles
inst "drac/rStarted" TIG;
inst "drac/rClrPll" TIG;
# It is OK for tristating of the data pins can take multiple clock cycles
inst "drac/READ" TIG;
# 20121011; OUT_TERM=UNTUNED_50 is too strong, use OUT_TERM=UNTUNED_25
Net ddq<0> LOC=W3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<1> LOC=W1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<2> LOC=U3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<3> LOC=T1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<4> LOC=Y2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<5> LOC=V2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<6> LOC=U1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<7> LOC=T2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<8> LOC=T4 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<9> LOC=R3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<10> LOC=M1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<11> LOC=L1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<12> LOC=T3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<13> LOC=R1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<14> LOC=M2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<15> LOC=L3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<16> LOC=K1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<17> LOC=K2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<18> LOC=H2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<19> LOC=G1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<20> LOC=M5 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<21> LOC=J3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddq<22> LOC=H1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<23> LOC=G3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<24> LOC=F1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<25> LOC=E1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<26> LOC=C3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<27> LOC=B2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<28> LOC=F3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<29> LOC=F2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<30> LOC=C1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<31> LOC=B1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddq<32> LOC=C22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<33> LOC=C20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<34> LOC=E20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<35> LOC=F22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<36> LOC=C19 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<37> LOC=D21 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<38> LOC=E22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<39> LOC=F21 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<40> LOC=G22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<41> LOC=H21 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<42> LOC=J20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<43> LOC=K21 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<44> LOC=F20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<45> LOC=G20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddq<46> LOC=J22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<47> LOC=K22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<48> LOC=L20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<49> LOC=M21 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<50> LOC=P21 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<51> LOC=R22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<52> LOC=L22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<53> LOC=M22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<54> LOC=P22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<55> LOC=R20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<56> LOC=T22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<57> LOC=U20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<58> LOC=V21 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<59> LOC=W22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<60> LOC=P19 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<61> LOC=T21 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<62> LOC=V22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddq<63> LOC=W20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net dqsp<0> LOC=U4 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net dqsp<1> LOC=N1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net dqsp<2> LOC=H3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net dqsp<3> LOC=D2 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net dqsp<4> LOC=D19 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net dqsp<5> LOC=J19 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net dqsp<6> LOC=N20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net dqsp<7> LOC=T19 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net dqsn<0> LOC=V3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net dqsn<1> LOC=N3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net dqsn<2> LOC=H4 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net dqsn<3> LOC=D1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net dqsn<4> LOC=D20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net dqsn<5> LOC=H20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net dqsn<6> LOC=N22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net dqsn<7> LOC=T20 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
#
# DM signals are outputs during writes and tristated at both ends during reads. We use parallel
# termination during reads on the assumption that it is better for the DM PCB traces not to float.
# It probably is not necessary, but it does not hurt.
#
Net ddm<0> LOC=V1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddm<1> LOC=P1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddm<2> LOC=J1 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LB
Net ddm<3> LOC=E3 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#LT
Net ddm<4> LOC=D22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddm<5> LOC=H22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RT
Net ddm<6> LOC=M19 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net ddm<7> LOC=U22 | IOSTANDARD=SSTL15_II | IN_TERM=UNTUNED_SPLIT_50 | OUT_TERM=UNTUNED_25;#RB
Net da<0> LOC=G19 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net da<1> LOC=A21 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net da<2> LOC=A20 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net da<3> LOC=A2 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<4> LOC=H8 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<5> LOC=G6 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<6> LOC=F5 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<7> LOC=G4 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<8> LOC=H6 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<9> LOC=J7 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<10> LOC=H19 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net da<11> LOC=H5 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<12> LOC=J6 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<13> LOC=M20 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RB
Net da<14> LOC=K4 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net da<15> LOC=K3 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net dba<0> LOC=J17 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net dba<1> LOC=H18 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net dba<2> LOC=J4 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net dcmd<2> LOC=K17 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT # RAS
Net dcmd<1> LOC=K18 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RB # CAS
Net dcmd<0> LOC=K20 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT # WE
Net dce<0> LOC=K5 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net dce<1> LOC=K6 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#LT
Net dcs<0> LOC=K19 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net dcs<1> LOC=L17 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RB
Net dckp<0> LOC=F18 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net dckp<1> LOC=B21 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net dckn<0> LOC=F19 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net dckn<1> LOC=B22 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RT
Net dodt<0> LOC=L19 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RB
Net dodt<1> LOC=P20 | IOSTANDARD=SSTL15_II | OUT_TERM=UNTUNED_25;#RB