Subversion Repositories debouncer_vhdl

Release 13.1 par O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

DEVELOP-W7::  Mon Aug 15 23:25:39 2011

par -w -intstyle ise -ol high -xe n -mt 4 debounce_atlys_top_map.ncd
debounce_atlys_top.ncd debounce_atlys_top.pcf 


Constraints file: debounce_atlys_top.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.
   "debounce_atlys_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.18 2011-04-07".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                    42 out of  54,576    1%
    Number used as Flip Flops:                  42
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                         37 out of  27,288    1%
    Number used as logic:                       36 out of  27,288    1%
      Number using O6 output only:              18
      Number using O5 output only:              11
      Number using O5 and O6:                    7
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   6,408    0%
    Number used exclusively as route-thrus:      1
      Number with same-slice register load:      0
      Number with same-slice carry load:         1
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                    19 out of   6,822    1%
  Number of LUT Flip Flop pairs used:           56
    Number with an unused Flip Flop:            20 out of      56   35%
    Number with an unused LUT:                  19 out of      56   33%
    Number of fully used LUT-FF pairs:          17 out of      56   30%
    Number of slice register sites lost
      to control set restrictions:               0 out of  54,576    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        31 out of     218   14%
    Number of LOCed IOBs:                       31 out of      31  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
    Number used as BUFGs:                        1
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router


Phase  1  : 199 unrouted;      REAL time: 5 secs 

Phase  2  : 168 unrouted;      REAL time: 5 secs 

Phase  3  : 46 unrouted;      REAL time: 6 secs 

Phase  4  : 46 unrouted; (Par is working to improve performance)     REAL time: 7 secs 

Updating file: debounce_atlys_top.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 7 secs 

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 7 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 7 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 7 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 7 secs 

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 7 secs 
Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 7 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net gcl | SETUP       |         N/A|     4.423ns|     N/A|           0
  k_i_BUFGP                                 | HOLD        |     0.424ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  261 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2

Writing design to file debounce_atlys_top.ncd



PAR done!