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https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk
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[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys_top_map.map] - Rev 8
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Release 13.1 Map O.40d (nt)
Xilinx Map Application Log File for Design 'debounce_atlys_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
off -o debounce_atlys_top_map.ncd debounce_atlys_top.ngd debounce_atlys_top.pcf
Target Device : xc6slx45
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Aug 15 23:25:20 2011
Running global optimization...
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 9 secs
Total CPU time at the beginning of Placer: 7 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:ed93dd56) REAL time: 11 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:ed93dd56) REAL time: 11 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:ed93dd56) REAL time: 11 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:feb5d5d6) REAL time: 13 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 13 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:feb5d5d6) REAL time: 13 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 13 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 13 secs
Phase 9.8 Global Placement
...
..
Phase 9.8 Global Placement (Checksum:6e34e131) REAL time: 13 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:6e34e131) REAL time: 13 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:ddc79b4e) REAL time: 13 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:ddc79b4e) REAL time: 13 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:d90e05db) REAL time: 13 secs
Total REAL time to Placer completion: 13 secs
Total CPU time to Placer completion: 10 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 42 out of 54,576 1%
Number used as Flip Flops: 42
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 37 out of 27,288 1%
Number used as logic: 36 out of 27,288 1%
Number using O6 output only: 18
Number using O5 output only: 11
Number using O5 and O6: 7
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 1
Number with same-slice register load: 0
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 19 out of 6,822 1%
Number of LUT Flip Flop pairs used: 56
Number with an unused Flip Flop: 20 out of 56 35%
Number with an unused LUT: 19 out of 56 33%
Number of fully used LUT-FF pairs: 17 out of 56 30%
Number of unique control sets: 3
Number of slice register sites lost
to control set restrictions: 6 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 31 out of 218 14%
Number of LOCed IOBs: 31 out of 31 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.37
Peak Memory Usage: 298 MB
Total REAL time to MAP completion: 15 secs
Total CPU time to MAP completion (all processors): 11 secs
Mapping completed.
See MAP report file "debounce_atlys_top_map.mrp" for details.