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# Design Specification
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# Author: Rudolf Usselmann
#         rudi@asics.ws
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# Revision:
# 5/10/01 RU Initial Sript
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# ==============================================
# Setup Design Parameters

set design_files {sbox2 sbox4 sbox6 sbox8 sbox1 sbox3 sbox5 sbox7 crp key_sel3 des3}

set design_name des3
set active_design des3
 
# Next Statement defines all clocks and resets in the design
set special_net {clk}
 
set hdl_src_dir {../../rtl/verilog/common ../../rtl/verilog/area_opt}