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[/] [des/] [trunk/] [syn/] [bin/] [read_ao3.dc] - Rev 7
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###############################################################################
#
# Pre Synthesis Script
#
# This script only reads in the design and saves it in a DB file
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
# ==============================================
# Setup Design Parameters
source ../bin/design_spec_ao3.dc
# ==============================================
# Setup Libraries
source ../bin/lib_spec.dc
# ==============================================
# Setup IO Files
append log_file ../log/$active_design "_pre.log"
append pre_comp_db_file ../out/$design_name "_pre.db"
sh rm -f $log_file
# ==============================================
# Setup Misc Variables
set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
# ==============================================
# Read Design
echo "+++++++++ Analyzing all design files ..." >> $log_file
foreach module $design_files {
echo "+++++++++ Reading: $module" >> $log_file
echo +++++++++ Reading: $module
set module_file_name ""
append module_file_name $module ".v"
analyze -f verilog $module_file_name >> $log_file
elaborate $module >> $log_file
}
current_design $active_design
echo "+++++++++ Linking Design ..." >> $log_file
link >> $log_file
echo "+++++++++ Uniquifying Design ..." >> $log_file
uniquify >> $log_file
echo "+++++++++ Checking Design ..." >> $log_file
check_design >> $log_file
# ==============================================
# Save Design
echo "+++++++++ Saving Design ..." >> $log_file
write_file -hierarchy -format db -output $pre_comp_db_file
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