OpenCores
URL https://opencores.org/ocsvn/diogenes/diogenes/trunk

Subversion Repositories diogenes

[/] [diogenes/] [tags/] [initial/] [diogenes/] [sim/] [sim] - Rev 236

Compare with Previous | Blame | View Log

t
UCTIION (former compare greater)                      storeio: 0x%02x->[0x%02x]
->PROGRAM-MEM address: 0x%04x (full 0x%08x) data: 0x%04x  (full: 0x%08x)
 Speicher:  %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x 
                           UART ad(%x): cannot open video ram file video.ram (VIDEO RAM unititialized!)pic%04d.tgaw+picture output fileLED: read from UART %2X
Unknown OperationUSAGE:
  sim <filename>
rBinary File '%s' not found
video.ram_DTOR_END____FRAME_END____JCR_END____do_global_ctors_aux/var/tmp/portage/sys-libs/glibc-2.5/work/build-default-i686-pc-linux-gnu-nptl/csu/crtn.Ssim.c_GLOBAL_OFFSET_TABLE___init_array_end__init_array_start_DYNAMICdata_startsprintf@@GLIBC_2.0headerPC__libc_csu_fini_startsim_graphicmem_dumpdecode__gmon_start___Jv_RegisterClasses_fp_hwregdump_finiRA__libc_start_main@@GLIBC_2.0_IO_getc@@GLIBC_2.0load_regSIMM6execute_IO_stdin_usedis_load__data_startloadedfclose@@GLIBC_2.1RBfopen@@GLIBC_2.1storeload__dso_handlefgetc@@GLIBC_2.0__libc_csu_initprintf@@GLIBC_2.0arithload_iobail_outfprintf@@GLIBC_2.0DMEM__bss_startpcolorglobal_vramRfputc@@GLIBC_2.0stdin@@GLIBC_2.0compare_endstdout@@GLIBC_2.0puts@@GLIBC_2.0specialbranchusagePMEM_IO_putc@@GLIBC_2.0IMM8fread@@GLIBC_2.0load_address_edataRDexit@@GLIBC_2.0bit_is_0__i686.get_pc_thunk.bxmain_initaddshift

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.