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[/] [diogenes/] [tags/] [initial/] [vhdl/] [_xmsgs/] [bitgen.xmsgs] - Rev 237
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="PhysDesignRules" num="812" delta="unknown" >Dangling pin <<arg fmt="%s" index="1">DOA14</arg>> on block:<<arg fmt="%s" index="2">diogenes_cpu/pipestage3/cdmem/B10/diogenes_cpu/pipestage3/cdmem/B10.A</arg>>:<<arg fmt="%s" index="3">RAMB16_RAMB16A</arg>>.
</msg>
<msg type="warning" file="PhysDesignRules" num="812" delta="unknown" >Dangling pin <<arg fmt="%s" index="1">DOA15</arg>> on block:<<arg fmt="%s" index="2">diogenes_cpu/pipestage3/cdmem/B10/diogenes_cpu/pipestage3/cdmem/B10.A</arg>>:<<arg fmt="%s" index="3">RAMB16_RAMB16A</arg>>.
</msg>
</messages>
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