URL
https://opencores.org/ocsvn/diogenes/diogenes/trunk
Subversion Repositories diogenes
[/] [diogenes/] [tags/] [initial/] [vhdl/] [_xmsgs/] [map.xmsgs] - Rev 236
Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">diogenes_cpu/pipestage2/rf/reg1/N1</arg> has no load.
</msg>
<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">136</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">diogenes_cpu/pipestage2/rf/reg1/N0,
diogenes_cpu/pipestage2/rf/reg1/BU2/qdpo<0>,
diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/qspo_int<31>,
diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/qspo_int<30>,
diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/qspo_int<29></arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>
<msg type="info" file="MapLib" num="863" delta="unknown" >The following Virtex BUFG(s) is/are being retargeted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFGP symbol "gclk_BUFGP" (output signal=gclk_BUFGP)</arg>
</msg>
<msg type="info" file="MapLib" num="159" delta="unknown" >Net Timing constraints on signal <arg fmt="%s" index="1">gclk</arg> are pushed forward through input buffer.
</msg>
<msg type="warning" file="PhysDesignRules" num="812" delta="unknown" >Dangling pin <<arg fmt="%s" index="1">DOA14</arg>> on block:<<arg fmt="%s" index="2">diogenes_cpu/pipestage3/cdmem/B10/diogenes_cpu/pipestage3/cdmem/B10.A</arg>>:<<arg fmt="%s" index="3">RAMB16_RAMB16A</arg>>.
</msg>
<msg type="warning" file="PhysDesignRules" num="812" delta="unknown" >Dangling pin <<arg fmt="%s" index="1">DOA15</arg>> on block:<<arg fmt="%s" index="2">diogenes_cpu/pipestage3/cdmem/B10/diogenes_cpu/pipestage3/cdmem/B10.A</arg>>:<<arg fmt="%s" index="3">RAMB16_RAMB16A</arg>>.
</msg>
</messages>