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https://opencores.org/ocsvn/diogenes/diogenes/trunk
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[/] [diogenes/] [tags/] [initial/] [vhdl/] [_xmsgs/] [vhpcomp.xmsgs] - Rev 114
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dist_mem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dmem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dist_mem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dmem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/pmem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dmem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dist_mem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dmem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dist_mem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dmem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/dist_mem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v3_2.vhd</arg>" first.
</msg>
<msg type="warning" file="HDLParsers" num="3583" delta="unknown" >File "<arg fmt="%s" index="1">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" which file "<arg fmt="%s" index="2">/home/andi/xilinx/rs232/cpu/pmem.vhd</arg>" depends on is modified, but has not been compiled. You may need to compile "<arg fmt="%s" index="3">/build/xfndry8/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/blkmemsp_v6_2.vhd</arg>" first.
</msg>
</messages>
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