URL
https://opencores.org/ocsvn/diogenes/diogenes/trunk
Subversion Repositories diogenes
[/] [diogenes/] [tags/] [initial/] [vhdl/] [cpu/] [dmem_readme.txt] - Rev 236
Compare with Previous | Blame | View Log
The following files were generated for 'dmem' in directory
/home/andi/coregen/:
dmem.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
dmem_readme.txt:
Text file indicating the files generated and how they are used.
dmem_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
dmem.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
dmem.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
dmem.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
dmem_xmdf.tcl:
Please see the core data sheet.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.