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URL https://opencores.org/ocsvn/diogenes/diogenes/trunk

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[/] [diogenes/] [tags/] [initial/] [vhdl/] [mysio.pcf] - Rev 237

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//! **************************************************************************
// Written by: Map J.36 on Mon Jan 28 21:05:20 2008
//! **************************************************************************

SCHEMATIC START;
COMP "strataflash_ce" LOCATE = SITE "D16" LEVEL 1;
COMP "strataflash_oe" LOCATE = SITE "C18" LEVEL 1;
COMP "strataflash_we" LOCATE = SITE "D17" LEVEL 1;
COMP "lcd_e" LOCATE = SITE "M18" LEVEL 1;
COMP "green" LOCATE = SITE "H15" LEVEL 1;
COMP "hs" LOCATE = SITE "F15" LEVEL 1;
COMP "rx" LOCATE = SITE "U8" LEVEL 1;
COMP "vs" LOCATE = SITE "F14" LEVEL 1;
COMP "tx" LOCATE = SITE "M13" LEVEL 1;
COMP "reset" LOCATE = SITE "L13" LEVEL 1;
COMP "lcd_rs" LOCATE = SITE "L18" LEVEL 1;
COMP "lcd_rw" LOCATE = SITE "L17" LEVEL 1;
COMP "gclk" LOCATE = SITE "C9" LEVEL 1;
COMP "blue" LOCATE = SITE "G15" LEVEL 1;
COMP "test<0>" LOCATE = SITE "F12" LEVEL 1;
COMP "test<1>" LOCATE = SITE "E12" LEVEL 1;
COMP "test<2>" LOCATE = SITE "E11" LEVEL 1;
COMP "test<3>" LOCATE = SITE "F11" LEVEL 1;
COMP "test<4>" LOCATE = SITE "C11" LEVEL 1;
COMP "test<5>" LOCATE = SITE "D11" LEVEL 1;
COMP "test<6>" LOCATE = SITE "E9" LEVEL 1;
COMP "test<7>" LOCATE = SITE "F9" LEVEL 1;
COMP "red" LOCATE = SITE "H14" LEVEL 1;
COMP "button<0>" LOCATE = SITE "H13" LEVEL 1;
COMP "button<1>" LOCATE = SITE "D18" LEVEL 1;
COMP "button<2>" LOCATE = SITE "K17" LEVEL 1;
COMP "button<3>" LOCATE = SITE "V4" LEVEL 1;
COMP "button<4>" LOCATE = SITE "K18" LEVEL 1;
COMP "button<5>" LOCATE = SITE "G18" LEVEL 1;
COMP "button<6>" LOCATE = SITE "V16" LEVEL 1;
COMP "button<7>" LOCATE = SITE "N17" LEVEL 1;
COMP "lcd_d<0>" LOCATE = SITE "R15" LEVEL 1;
COMP "lcd_d<1>" LOCATE = SITE "R16" LEVEL 1;
COMP "lcd_d<2>" LOCATE = SITE "P17" LEVEL 1;
COMP "lcd_d<3>" LOCATE = SITE "M15" LEVEL 1;
NET "gclk_BUFGP/IBUFG" BEL "gclk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
PIN pmemc/B6.A_pins<15> = BEL "pmemc/B6.A" PINNAME CLKA;
PIN pmemc/B6.B_pins<15> = BEL "pmemc/B6.B" PINNAME CLKB;
PIN vga_c/video_ram_c/B6.A_pins<15> = BEL "vga_c/video_ram_c/B6.A" PINNAME
        CLKA;
PIN vga_c/video_ram_c/B6.B_pins<15> = BEL "vga_c/video_ram_c/B6.B" PINNAME
        CLKB;
PIN vga_c/video_ram_c/B10.A_pins<15> = BEL "vga_c/video_ram_c/B10.A" PINNAME
        CLKA;
PIN vga_c/video_ram_c/B10.B_pins<15> = BEL "vga_c/video_ram_c/B10.B" PINNAME
        CLKB;
PIN vga_c/video_ram_c/B14.A_pins<15> = BEL "vga_c/video_ram_c/B14.A" PINNAME
        CLKA;
PIN vga_c/video_ram_c/B14.B_pins<15> = BEL "vga_c/video_ram_c/B14.B" PINNAME
        CLKB;
PIN vga_c/video_ram_c/B18.A_pins<15> = BEL "vga_c/video_ram_c/B18.A" PINNAME
        CLKA;
PIN vga_c/video_ram_c/B18.B_pins<15> = BEL "vga_c/video_ram_c/B18.B" PINNAME
        CLKB;
TIMEGRP gclk = BEL "was_button" BEL "pmem_addr_m_0" BEL "pmem_addr_m_1" BEL
        "pmem_addr_m_2" BEL "pmem_addr_m_3" BEL "pmem_addr_m_4" BEL
        "pmem_addr_m_5" BEL "pmem_addr_m_6" BEL "pmem_addr_m_7" BEL
        "pmem_addr_m_8" BEL "pmem_addr_m_9" BEL "pmem_din_m_0" BEL
        "pmem_din_m_1" BEL "pmem_din_m_2" BEL "pmem_din_m_3" BEL
        "pmem_din_m_4" BEL "pmem_din_m_5" BEL "pmem_din_m_6" BEL
        "pmem_din_m_7" BEL "pmem_din_m_8" BEL "pmem_din_m_9" BEL
        "pmem_din_m_10" BEL "pmem_din_m_11" BEL "pmem_din_m_12" BEL
        "pmem_din_m_13" BEL "pmem_din_m_14" BEL "pmem_din_m_15" BEL
        "vmem_we_m" BEL "pmem_we_m" BEL "was_uart" BEL "vmem_addr_m_0" BEL
        "vmem_addr_m_1" BEL "vmem_addr_m_2" BEL "vmem_addr_m_3" BEL
        "vmem_addr_m_4" BEL "vmem_addr_m_5" BEL "vmem_addr_m_6" BEL
        "vmem_addr_m_7" BEL "vmem_addr_m_8" BEL "vmem_addr_m_9" BEL
        "vmem_addr_m_10" BEL "vmem_addr_m_11" BEL "vmem_addr_m_12" BEL
        "lcd_rs_l" BEL "test_led_0" BEL "test_led_1" BEL "test_led_2" BEL
        "test_led_3" BEL "test_led_4" BEL "test_led_5" BEL "test_led_6" BEL
        "test_led_7" BEL "lcd_rw_l" BEL "vmem_din_m_0" BEL "vmem_din_m_1" BEL
        "vmem_din_m_2" BEL "vmem_din_m_3" BEL "vmem_din_m_4" BEL
        "vmem_din_m_5" BEL "vmem_din_m_6" BEL "vmem_din_m_7" BEL "lcd_d_l_0"
        BEL "lcd_d_l_1" BEL "lcd_d_l_2" BEL "lcd_d_l_3" BEL "lcd_e_l" PIN
        "pmemc/B6.A_pins<15>" PIN "pmemc/B6.B_pins<15>" BEL
        "diogenes_cpu/pipestage1/pc_31" BEL "diogenes_cpu/pipestage1/pc_30"
        BEL "diogenes_cpu/pipestage1/pc_29" BEL
        "diogenes_cpu/pipestage1/pc_28" BEL "diogenes_cpu/pipestage1/pc_27"
        BEL "diogenes_cpu/pipestage1/pc_26" BEL
        "diogenes_cpu/pipestage1/pc_25" BEL "diogenes_cpu/pipestage1/pc_24"
        BEL "diogenes_cpu/pipestage1/pc_23" BEL
        "diogenes_cpu/pipestage1/pc_22" BEL "diogenes_cpu/pipestage1/pc_21"
        BEL "diogenes_cpu/pipestage1/pc_20" BEL
        "diogenes_cpu/pipestage1/pc_19" BEL "diogenes_cpu/pipestage1/pc_18"
        BEL "diogenes_cpu/pipestage1/pc_17" BEL
        "diogenes_cpu/pipestage1/pc_16" BEL "diogenes_cpu/pipestage1/pc_15"
        BEL "diogenes_cpu/pipestage1/pc_14" BEL
        "diogenes_cpu/pipestage1/pc_13" BEL "diogenes_cpu/pipestage1/pc_12"
        BEL "diogenes_cpu/pipestage1/pc_11" BEL
        "diogenes_cpu/pipestage1/pc_10" BEL "diogenes_cpu/pipestage1/pc_9" BEL
        "diogenes_cpu/pipestage1/pc_8" BEL "diogenes_cpu/pipestage1/pc_7" BEL
        "diogenes_cpu/pipestage1/pc_6" BEL "diogenes_cpu/pipestage1/pc_5" BEL
        "diogenes_cpu/pipestage1/pc_4" BEL "diogenes_cpu/pipestage1/pc_3" BEL
        "diogenes_cpu/pipestage1/pc_2" BEL "diogenes_cpu/pipestage1/pc_1" BEL
        "diogenes_cpu/pipestage1/pc_0" BEL "diogenes_cpu/pipestage1/curpc_9"
        BEL "diogenes_cpu/pipestage1/curpc_8" BEL
        "diogenes_cpu/pipestage1/curpc_7" BEL
        "diogenes_cpu/pipestage1/curpc_6" BEL
        "diogenes_cpu/pipestage1/curpc_5" BEL
        "diogenes_cpu/pipestage1/curpc_3" BEL
        "diogenes_cpu/pipestage1/curpc_2" BEL
        "diogenes_cpu/pipestage1/curpc_4" BEL
        "diogenes_cpu/pipestage1/curpc_1" BEL
        "diogenes_cpu/pipestage1/curpc_0" BEL "diogenes_cpu/pipestage1/first"
        BEL "vga_c/vertical_counter_9" BEL "vga_c/vertical_counter_8" BEL
        "vga_c/vertical_counter_7" BEL "vga_c/vertical_counter_6" BEL
        "vga_c/vertical_counter_5" BEL "vga_c/vertical_counter_4" BEL
        "vga_c/vertical_counter_3" BEL "vga_c/vertical_counter_2" BEL
        "vga_c/vertical_counter_1" BEL "vga_c/vertical_counter_0" BEL
        "vga_c/horizontal_counter_9" BEL "vga_c/horizontal_counter_8" BEL
        "vga_c/horizontal_counter_7" BEL "vga_c/horizontal_counter_6" BEL
        "vga_c/horizontal_counter_5" BEL "vga_c/horizontal_counter_4" BEL
        "vga_c/horizontal_counter_3" BEL "vga_c/horizontal_counter_2" BEL
        "vga_c/horizontal_counter_1" BEL "vga_c/horizontal_counter_0" BEL
        "vga_c/hs_out" BEL "vga_c/vs_out" BEL "vga_c/green_out" BEL
        "vga_c/blue_out" BEL "vga_c/v_addr_12" BEL "vga_c/v_addr_11" BEL
        "vga_c/v_addr_10" BEL "vga_c/v_addr_9" BEL "vga_c/v_addr_8" BEL
        "vga_c/v_addr_7" BEL "vga_c/v_addr_6" BEL "vga_c/v_addr_5" BEL
        "vga_c/v_addr_4" BEL "vga_c/v_addr_3" BEL "vga_c/v_addr_2" BEL
        "vga_c/v_addr_1" BEL "vga_c/v_addr_0" BEL "vga_c/red_out" BEL
        "vga_c/clk25" BEL "vga_c/pixel_2" BEL "vga_c/pixel_1" BEL
        "vga_c/pixel_0" BEL "vga_c/pixel_buf_2" BEL "vga_c/pixel_buf_1" BEL
        "vga_c/pixel_buf_0" BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem63.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem63.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem61.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem61.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem59.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem59.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem57.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem57.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem55.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem55.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem53.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem53.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem51.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem51.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem49.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem49.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem47.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem47.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem45.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem45.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem43.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem43.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem41.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem41.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem39.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem39.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem37.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem37.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem35.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem35.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem33.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem33.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem31.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem31.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem29.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem29.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem27.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem27.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem25.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem25.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem23.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem23.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem21.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem21.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem19.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem19.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem17.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem17.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem15.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem15.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem13.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem13.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem11.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem11.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem9.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem9.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem7.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem7.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem5.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem5.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem3.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem3.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem1.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem1.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem63.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem63.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem61.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem61.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem59.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem59.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem57.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem57.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem55.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem55.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem53.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem53.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem51.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem51.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem49.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem49.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem47.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem47.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem45.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem45.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem43.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem43.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem41.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem41.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem39.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem39.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem37.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem37.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem35.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem35.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem33.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem33.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem31.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem31.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem29.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem29.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem27.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem27.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem25.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem25.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem23.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem23.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem21.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem21.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem19.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem19.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem17.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem17.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem15.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem15.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem13.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem13.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem11.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem11.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem9.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem9.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem7.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem7.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem5.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem5.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem3.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem3.SLICEM_G"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem1.SLICEM_F"
        BEL
        "diogenes_cpu/pipestage2/rf/reg2/BU2/U0/gen_dp_ram.dpram_inst/inst_Mram_mem1.SLICEM_G"
        BEL "diogenes_cpu/pipestage2/brzero_1" BEL
        "diogenes_cpu/pipestage2/brzero_0" BEL
        "diogenes_cpu/pipestage2/big_op_14" BEL
        "diogenes_cpu/pipestage2/big_op_13" BEL
        "diogenes_cpu/pipestage2/big_op_12" BEL
        "diogenes_cpu/pipestage2/big_op_11" BEL
        "diogenes_cpu/pipestage2/big_op_8" BEL
        "diogenes_cpu/pipestage2/big_op_7" BEL
        "diogenes_cpu/pipestage2/big_op_6" BEL
        "diogenes_cpu/pipestage2/big_op_5" BEL
        "diogenes_cpu/pipestage2/big_op_4" BEL
        "diogenes_cpu/pipestage2/big_op_3" BEL
        "diogenes_cpu/pipestage2/big_op_2" BEL
        "diogenes_cpu/pipestage2/big_op_1" BEL
        "diogenes_cpu/pipestage2/big_op_0" BEL
        "diogenes_cpu/pipestage2/sop2_30" BEL
        "diogenes_cpu/pipestage2/sop2_25" BEL "diogenes_cpu/pipestage2/sop2_2"
        BEL "diogenes_cpu/pipestage2/sop2_19" BEL
        "diogenes_cpu/pipestage2/sop2_1" BEL "diogenes_cpu/pipestage2/sop2_24"
        BEL "diogenes_cpu/pipestage2/sop2_23" BEL
        "diogenes_cpu/pipestage2/sop2_18" BEL "diogenes_cpu/pipestage2/fwop2"
        BEL "diogenes_cpu/pipestage2/fwop1" BEL
        "diogenes_cpu/pipestage2/sop2_0" BEL "diogenes_cpu/pipestage2/sop2_22"
        BEL "diogenes_cpu/pipestage2/sop2_17" BEL
        "diogenes_cpu/pipestage2/sop2_16" BEL
        "diogenes_cpu/pipestage2/sop2_20" BEL
        "diogenes_cpu/pipestage2/sop2_21" BEL
        "diogenes_cpu/pipestage2/sop2_15" BEL
        "diogenes_cpu/pipestage2/sop1_29" BEL
        "diogenes_cpu/pipestage2/sop1_28" BEL
        "diogenes_cpu/pipestage2/sop2_13" BEL
        "diogenes_cpu/pipestage2/sop2_14" BEL
        "diogenes_cpu/pipestage2/sop1_27" BEL
        "diogenes_cpu/pipestage2/sop2_12" BEL
        "diogenes_cpu/pipestage2/sop1_26" BEL
        "diogenes_cpu/pipestage2/sop2_11" BEL
        "diogenes_cpu/pipestage2/sop1_31" BEL
        "diogenes_cpu/pipestage2/sop1_30" BEL
        "diogenes_cpu/pipestage2/sop1_25" BEL
        "diogenes_cpu/pipestage2/lastdest_3" BEL
        "diogenes_cpu/pipestage2/lastdest_2" BEL
        "diogenes_cpu/pipestage2/lastdest_1" BEL
        "diogenes_cpu/pipestage2/lastdest_0" BEL
        "diogenes_cpu/pipestage2/sop1_24" BEL
        "diogenes_cpu/pipestage2/sop2_10" BEL
        "diogenes_cpu/pipestage2/sop1_19" BEL
        "diogenes_cpu/pipestage2/sop1_23" BEL
        "diogenes_cpu/pipestage2/sop1_22" BEL
        "diogenes_cpu/pipestage2/sop1_17" BEL
        "diogenes_cpu/pipestage2/sop1_18" BEL
        "diogenes_cpu/pipestage2/sop1_21" BEL
        "diogenes_cpu/pipestage2/sop1_16" BEL
        "diogenes_cpu/pipestage2/sop1_15" BEL
        "diogenes_cpu/pipestage2/sop1_14" BEL
        "diogenes_cpu/pipestage2/sop1_20" BEL
        "diogenes_cpu/pipestage2/sop1_13" BEL
        "diogenes_cpu/pipestage2/sop1_12" BEL "diogenes_cpu/pipestage2/sop1_9"
        BEL "diogenes_cpu/pipestage2/sop1_10" BEL
        "diogenes_cpu/pipestage2/sop1_11" BEL "diogenes_cpu/pipestage2/sop1_8"
        BEL "diogenes_cpu/pipestage2/newpc_31" BEL
        "diogenes_cpu/pipestage2/newpc_30" BEL
        "diogenes_cpu/pipestage2/newpc_29" BEL
        "diogenes_cpu/pipestage2/newpc_28" BEL
        "diogenes_cpu/pipestage2/newpc_27" BEL
        "diogenes_cpu/pipestage2/newpc_26" BEL
        "diogenes_cpu/pipestage2/newpc_25" BEL
        "diogenes_cpu/pipestage2/newpc_24" BEL
        "diogenes_cpu/pipestage2/newpc_23" BEL
        "diogenes_cpu/pipestage2/newpc_22" BEL
        "diogenes_cpu/pipestage2/newpc_21" BEL
        "diogenes_cpu/pipestage2/newpc_20" BEL
        "diogenes_cpu/pipestage2/newpc_19" BEL
        "diogenes_cpu/pipestage2/newpc_18" BEL
        "diogenes_cpu/pipestage2/newpc_17" BEL
        "diogenes_cpu/pipestage2/newpc_16" BEL
        "diogenes_cpu/pipestage2/newpc_15" BEL
        "diogenes_cpu/pipestage2/newpc_14" BEL
        "diogenes_cpu/pipestage2/newpc_13" BEL
        "diogenes_cpu/pipestage2/newpc_12" BEL
        "diogenes_cpu/pipestage2/newpc_11" BEL
        "diogenes_cpu/pipestage2/newpc_10" BEL
        "diogenes_cpu/pipestage2/newpc_9" BEL
        "diogenes_cpu/pipestage2/newpc_8" BEL
        "diogenes_cpu/pipestage2/newpc_7" BEL
        "diogenes_cpu/pipestage2/newpc_6" BEL
        "diogenes_cpu/pipestage2/newpc_5" BEL
        "diogenes_cpu/pipestage2/newpc_4" BEL
        "diogenes_cpu/pipestage2/newpc_3" BEL
        "diogenes_cpu/pipestage2/newpc_2" BEL
        "diogenes_cpu/pipestage2/newpc_1" BEL
        "diogenes_cpu/pipestage2/newpc_0" BEL "diogenes_cpu/pipestage2/sop1_6"
        BEL "diogenes_cpu/pipestage2/sop1_5" BEL
        "diogenes_cpu/pipestage2/sop1_7" BEL "diogenes_cpu/pipestage2/sop1_4"
        BEL "diogenes_cpu/pipestage2/fwshiftop" BEL
        "diogenes_cpu/pipestage2/sop1_2" BEL "diogenes_cpu/pipestage2/sop1_1"
        BEL "diogenes_cpu/pipestage2/sop1_3" BEL
        "diogenes_cpu/pipestage2/sop1_0" BEL "diogenes_cpu/pipestage2/sop2_9"
        BEL "diogenes_cpu/pipestage2/sop2_7" BEL
        "diogenes_cpu/pipestage2/fw_pc" BEL "diogenes_cpu/pipestage2/sop2_8"
        BEL "diogenes_cpu/pipestage2/sop2_29" BEL
        "diogenes_cpu/pipestage2/sop2_6" BEL "diogenes_cpu/pipestage2/sop2_5"
        BEL "diogenes_cpu/pipestage2/sop2_27" BEL
        "diogenes_cpu/pipestage2/sop2_28" BEL "diogenes_cpu/pipestage2/sop2_4"
        BEL "diogenes_cpu/pipestage2/sop2_31" BEL
        "diogenes_cpu/pipestage2/sop2_3" BEL "diogenes_cpu/pipestage2/sop2_26"
        BEL "sc_uartc/clktx_3" BEL "sc_uartc/clktx_2" BEL "sc_uartc/clktx_1"
        BEL "sc_uartc/clktx_0" BEL "sc_uartc/clkrx_3" BEL "sc_uartc/clkrx_2"
        BEL "sc_uartc/clkrx_1" BEL "sc_uartc/clkrx_0" BEL "sc_uartc/i_3" BEL
        "sc_uartc/i_2" BEL "sc_uartc/i_1" BEL "sc_uartc/i_0" BEL
        "sc_uartc/clk16_31" BEL "sc_uartc/clk16_30" BEL "sc_uartc/clk16_29"
        BEL "sc_uartc/clk16_28" BEL "sc_uartc/clk16_27" BEL
        "sc_uartc/clk16_26" BEL "sc_uartc/clk16_25" BEL "sc_uartc/clk16_24"
        BEL "sc_uartc/clk16_23" BEL "sc_uartc/clk16_22" BEL
        "sc_uartc/clk16_21" BEL "sc_uartc/clk16_20" BEL "sc_uartc/clk16_19"
        BEL "sc_uartc/clk16_18" BEL "sc_uartc/clk16_17" BEL
        "sc_uartc/clk16_16" BEL "sc_uartc/clk16_15" BEL "sc_uartc/clk16_14"
        BEL "sc_uartc/clk16_13" BEL "sc_uartc/clk16_12" BEL
        "sc_uartc/clk16_11" BEL "sc_uartc/clk16_10" BEL "sc_uartc/clk16_9" BEL
        "sc_uartc/clk16_8" BEL "sc_uartc/clk16_7" BEL "sc_uartc/clk16_6" BEL
        "sc_uartc/clk16_5" BEL "sc_uartc/clk16_4" BEL "sc_uartc/clk16_3" BEL
        "sc_uartc/clk16_2" BEL "sc_uartc/clk16_1" BEL "sc_uartc/clk16_0" BEL
        "sc_uartc/uart_rx_state_FFd1" BEL "sc_uartc/uart_rx_state_FFd2" BEL
        "sc_uartc/cmp_tf/g1[0].f1/f" BEL "sc_uartc/cmp_tf/g1[0].f1/buf_7" BEL
        "sc_uartc/cmp_tf/g1[0].f1/buf_6" BEL "sc_uartc/cmp_tf/g1[0].f1/buf_5"
        BEL "sc_uartc/cmp_tf/g1[0].f1/buf_4" BEL
        "sc_uartc/cmp_tf/g1[0].f1/buf_3" BEL "sc_uartc/cmp_tf/g1[0].f1/buf_2"
        BEL "sc_uartc/cmp_tf/g1[0].f1/buf_1" BEL
        "sc_uartc/cmp_tf/g1[0].f1/buf_0" BEL "sc_uartc/cmp_rf/g1[0].f1/f" BEL
        "sc_uartc/cmp_rf/g1[0].f1/buf_7" BEL "sc_uartc/cmp_rf/g1[0].f1/buf_6"
        BEL "sc_uartc/cmp_rf/g1[0].f1/buf_5" BEL
        "sc_uartc/cmp_rf/g1[0].f1/buf_4" BEL "sc_uartc/cmp_rf/g1[0].f1/buf_3"
        BEL "sc_uartc/cmp_rf/g1[0].f1/buf_2" BEL
        "sc_uartc/cmp_rf/g1[0].f1/buf_1" BEL "sc_uartc/cmp_rf/g1[0].f1/buf_0"
        BEL "sc_uartc/rsr_0" BEL "sc_uartc/rsr_1" BEL "sc_uartc/rsr_2" BEL
        "sc_uartc/rsr_3" BEL "sc_uartc/rsr_4" BEL "sc_uartc/rsr_5" BEL
        "sc_uartc/rsr_6" BEL "sc_uartc/rsr_7" BEL "sc_uartc/rsr_8" BEL
        "sc_uartc/rsr_9" BEL "sc_uartc/rx_buf_2" BEL "sc_uartc/rx_buf_1" BEL
        "sc_uartc/rx_buf_0" BEL "sc_uartc/ncts_buf_2" BEL
        "sc_uartc/ncts_buf_1" BEL "sc_uartc/tsr_6" BEL "sc_uartc/tsr_5" BEL
        "sc_uartc/i0_3" BEL "sc_uartc/i0_2" BEL "sc_uartc/i0_1" BEL
        "sc_uartc/i0_0" BEL "sc_uartc/tsr_4" BEL "sc_uartc/tsr_3" BEL
        "sc_uartc/tsr_2" BEL "sc_uartc/tsr_1" BEL "sc_uartc/tsr_0" BEL
        "sc_uartc/tx_clk" BEL "sc_uartc/uart_tx_state_0" BEL "sc_uartc/tf_rd"
        BEL "sc_uartc/ncts_buf_0" BEL "sc_uartc/rx_clk_ena" BEL
        "sc_uartc/rf_wr" BEL "sc_uartc/rx_clk" BEL "sc_uartc/tsr_8" BEL
        "sc_uartc/tsr_9" BEL "sc_uartc/tsr_7" BEL
        "diogenes_cpu/pipestage3/calu/s_0" BEL
        "diogenes_cpu/pipestage3/calu/s_1" BEL
        "diogenes_cpu/pipestage3/calu/s_2" BEL
        "diogenes_cpu/pipestage3/calu/s_3" BEL
        "diogenes_cpu/pipestage3/calu/s_4" BEL
        "diogenes_cpu/pipestage3/calu/s_5" BEL
        "diogenes_cpu/pipestage3/calu/s_6" BEL
        "diogenes_cpu/pipestage3/calu/s_7" BEL
        "diogenes_cpu/pipestage3/calu/s_8" BEL
        "diogenes_cpu/pipestage3/calu/s_9" BEL
        "diogenes_cpu/pipestage3/calu/s_10" BEL
        "diogenes_cpu/pipestage3/calu/s_11" BEL
        "diogenes_cpu/pipestage3/calu/s_12" BEL
        "diogenes_cpu/pipestage3/calu/s_13" BEL
        "diogenes_cpu/pipestage3/calu/s_14" BEL
        "diogenes_cpu/pipestage3/calu/s_15" BEL
        "diogenes_cpu/pipestage3/calu/s_16" BEL
        "diogenes_cpu/pipestage3/calu/s_17" BEL
        "diogenes_cpu/pipestage3/calu/s_18" BEL
        "diogenes_cpu/pipestage3/calu/s_19" BEL
        "diogenes_cpu/pipestage3/calu/s_20" BEL
        "diogenes_cpu/pipestage3/calu/s_21" BEL
        "diogenes_cpu/pipestage3/calu/s_22" BEL
        "diogenes_cpu/pipestage3/calu/s_23" BEL
        "diogenes_cpu/pipestage3/calu/s_24" BEL
        "diogenes_cpu/pipestage3/calu/s_25" BEL
        "diogenes_cpu/pipestage3/calu/s_26" BEL
        "diogenes_cpu/pipestage3/calu/s_27" BEL
        "diogenes_cpu/pipestage3/calu/s_28" BEL
        "diogenes_cpu/pipestage3/calu/s_29" BEL
        "diogenes_cpu/pipestage3/calu/s_30" BEL
        "diogenes_cpu/pipestage3/calu/s_31" BEL
        "diogenes_cpu/pipestage3/cdmem/B6.A" BEL
        "diogenes_cpu/pipestage3/cdmem/B10.A" BEL
        "diogenes_cpu/pipestage3/wasmem" BEL "diogenes_cpu/pipestage3/wasext"
        BEL "diogenes_cpu/pipestage3/regaddr_3" BEL
        "diogenes_cpu/pipestage3/regaddr_2" BEL
        "diogenes_cpu/pipestage3/regaddr_1" BEL
        "diogenes_cpu/pipestage3/regaddr_0" BEL
        "diogenes_cpu/pipestage1/first_1" BEL
        "diogenes_cpu/pipestage2/fwop2_1" BEL
        "diogenes_cpu/pipestage2/fwshiftop_1" BEL
        "diogenes_cpu/pipestage2/fwshiftop_2" BEL
        "diogenes_cpu/pipestage2/fwshiftop_3" BEL
        "diogenes_cpu/pipestage2/fwop1_1" BEL "sc_uartc/Mshreg_rxd_reg_2" BEL
        "sc_uartc/rxd_reg_2" PIN "vga_c/video_ram_c/B6.A_pins<15>" PIN
        "vga_c/video_ram_c/B6.B_pins<15>" PIN
        "vga_c/video_ram_c/B10.A_pins<15>" PIN
        "vga_c/video_ram_c/B10.B_pins<15>" PIN
        "vga_c/video_ram_c/B14.A_pins<15>" PIN
        "vga_c/video_ram_c/B14.B_pins<15>" PIN
        "vga_c/video_ram_c/B18.A_pins<15>" PIN
        "vga_c/video_ram_c/B18.B_pins<15>";
NET "gclk_BUFGP/IBUFG" PERIOD = 12 ns HIGH 50%;
SCHEMATIC END;

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