Subversion Repositories diogenes

Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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Reading design: mysio.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "mysio.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "mysio"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : mysio
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : mysio.lso
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/types.vhd" in Library work.
Architecture types of Entity types is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/barrel.vhd" in Library work.
Architecture behavioral of Entity barrel is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.vhd" in Library work.
Architecture dist_mem_a of Entity dist_mem is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/dmem.vhd" in Library work.
Architecture dmem_a of Entity dmem is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/alu.vhd" in Library work.
Architecture behavioral of Entity alu is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" in Library work.
Architecture behavioral of Entity regfile is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/fetch.vhd" in Library work.
Architecture behavioral of Entity fetch is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd" in Library work.
Architecture behavioral of Entity decode is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd" in Library work.
Architecture behavioral of Entity execute is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/fifo.vhd" in Library work.
Architecture rtl of Entity fifo_elem is up to date.
Architecture rtl of Entity fifo is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/video_ram.vhd" in Library work.
Architecture video_ram_a of Entity video_ram is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl" in Library work.
Architecture behavioral of Entity vga is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/sc_uart.vhd" in Library work.
Architecture rtl of Entity sc_uart is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/pmem.vhd" in Library work.
Architecture pmem_a of Entity pmem is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/cpu.vhd" in Library work.
Architecture behavioral of Entity cpu is up to date.
Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/sio.vhd" in Library work.
Architecture behavioral of Entity mysio is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <mysio> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <vga> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <sc_uart> in library <work> (architecture <rtl>) with generics.
        addr_bits = 1
        baud_rate = 115000
        clk_freq = 50000000
        rxf_depth = 1
        rxf_thres = 1
        txf_depth = 1
        txf_thres = 1

Analyzing hierarchy for entity <cpu> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <fifo> in library <work> (architecture <rtl>) with generics.
        depth = 1
        thres = 1
        width = 8

Analyzing hierarchy for entity <fetch> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <decode> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <execute> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <fifo_elem> in library <work> (architecture <rtl>) with generics.
        width = 8

Analyzing hierarchy for entity <regfile> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <alu> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <barrel> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mysio> in library <work> (Architecture <behavioral>).
WARNING:Xst:753 - "/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 219: Unconnected output port 'nrts' of component 'sc_uart'.
WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 237: Instantiating black box module <pmem>.
WARNING:Xst:819 - "/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 273: The following signals are missing in the process sensitivity list:
   was_uart, was_button, button.
Entity <mysio> analyzed. Unit <mysio> generated.

Analyzing Entity <vga> in library <work> (Architecture <behavioral>).
WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl" line 51: Instantiating black box module <video_ram>.
Entity <vga> analyzed. Unit <vga> generated.

Analyzing generic Entity <sc_uart> in library <work> (Architecture <rtl>).
        addr_bits = 1
        baud_rate = 115000
        clk_freq = 50000000
        rxf_depth = 1
        rxf_thres = 1
        txf_depth = 1
        txf_thres = 1
Entity <sc_uart> analyzed. Unit <sc_uart> generated.

Analyzing generic Entity <fifo> in library <work> (Architecture <rtl>).
        depth = 1
        thres = 1
        width = 8
Entity <fifo> analyzed. Unit <fifo> generated.

Analyzing generic Entity <fifo_elem> in library <work> (Architecture <rtl>).
        width = 8
Entity <fifo_elem> analyzed. Unit <fifo_elem> generated.

Analyzing Entity <cpu> in library <work> (Architecture <behavioral>).
Entity <cpu> analyzed. Unit <cpu> generated.

Analyzing Entity <fetch> in library <work> (Architecture <behavioral>).
INFO:Xst:2679 - Register <curpc<31>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<30>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<29>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<28>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<27>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<26>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<25>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<24>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<23>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<22>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<21>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<20>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<19>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<18>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<17>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<16>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<15>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<14>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<13>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<12>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<11>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <curpc<10>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <fetch> analyzed. Unit <fetch> generated.

Analyzing Entity <decode> in library <work> (Architecture <behavioral>).
INFO:Xst:1561 - "/home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd" line 191: Mux is complete : default of case is discarded
Entity <decode> analyzed. Unit <decode> generated.

Analyzing Entity <regfile> in library <work> (Architecture <behavioral>).
WARNING:Xst:753 - "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 64: Unconnected output port 'spo' of component 'dist_mem'.
WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 64: Instantiating black box module <dist_mem>.
WARNING:Xst:753 - "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 74: Unconnected output port 'spo' of component 'dist_mem'.
WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 74: Instantiating black box module <dist_mem>.
Entity <regfile> analyzed. Unit <regfile> generated.

Analyzing Entity <execute> in library <work> (Architecture <behavioral>).
WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd" line 96: Instantiating black box module <dmem>.
Entity <execute> analyzed. Unit <execute> generated.

Analyzing Entity <alu> in library <work> (Architecture <behavioral>).
Entity <alu> analyzed. Unit <alu> generated.

Analyzing Entity <barrel> in library <work> (Architecture <behavioral>).
Entity <barrel> analyzed. Unit <barrel> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <fifo_elem>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/fifo.vhd".
    Found 1-bit register for signal <rd_prev>.
    Found 8-bit register for signal <buf>.
    Found 1-bit register for signal <f>.
    Summary:
        inferred  10 D-type flip-flop(s).
Unit <fifo_elem> synthesized.


Synthesizing Unit <fetch>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/fetch.vhd".
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
    Found 32-bit register for signal <pc>.
    Found 32-bit 4-to-1 multiplexer for signal <cpc>.
    Found 10-bit register for signal <curpc<9:0>>.
    Found 10-bit adder for signal <curpc_9_0$add0000> created at line 85.
    Found 1-bit register for signal <first>.
    Summary:
        inferred  43 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  32 Multiplexer(s).
Unit <fetch> synthesized.


Synthesizing Unit <barrel>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/barrel.vhd".
    Found 32-bit shifter logical left for signal <l1>.
    Found 32-bit 4-to-1 multiplexer for signal <l2>.
    Found 32-bit shifter logical right for signal <r1>.
    Found 32-bit 4-to-1 multiplexer for signal <r2>.
    Summary:
        inferred  64 Multiplexer(s).
        inferred   2 Combinational logic shifter(s).
Unit <barrel> synthesized.


Synthesizing Unit <vga>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl".
WARNING:Xst:646 - Signal <pixel_buf<7:4>> is assigned but never used.
WARNING:Xst:1780 - Signal <count> is never used or assigned.
WARNING:Xst:646 - Signal <pixel<3>> is assigned but never used.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
    Found 1-bit register for signal <blue_out>.
    Found 1-bit register for signal <red_out>.
    Found 1-bit register for signal <vs_out>.
    Found 1-bit register for signal <green_out>.
    Found 1-bit register for signal <hs_out>.
    Found 1-bit register for signal <clk25>.
    Found 10-bit up counter for signal <horizontal_counter>.
    Found 10-bit comparator greater for signal <hs_out$cmp_gt0000> created at line 98.
    Found 10-bit comparator less for signal <hs_out$cmp_lt0000> created at line 98.
    Found 4-bit register for signal <pixel>.
    Found 8-bit register for signal <pixel_buf>.
    Found 10-bit comparator less for signal <red_out$cmp_lt0000> created at line 86.
    Found 10-bit comparator less for signal <red_out$cmp_lt0001> created at line 86.
    Found 10-bit adder for signal <temp$add0000> created at line 127.
    Found 10-bit adder for signal <temp$add0001> created at line 132.
    Found 13-bit register for signal <v_addr>.
    Found 10-bit up counter for signal <vertical_counter>.
    Found 10-bit comparator greater for signal <vs_out$cmp_gt0000> created at line 104.
    Found 10-bit comparator less for signal <vs_out$cmp_lt0000> created at line 104.
    Summary:
        inferred   2 Counter(s).
        inferred  31 D-type flip-flop(s).
        inferred   2 Adder/Subtractor(s).
        inferred   6 Comparator(s).
Unit <vga> synthesized.


Synthesizing Unit <fifo>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/fifo.vhd".
WARNING:Xst:646 - Signal <rp<0>> is assigned but never used.
Unit <fifo> synthesized.


Synthesizing Unit <regfile>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd".
WARNING:Xst:647 - Input <reset> is never used.
    Found 5-bit comparator equal for signal <dout1$cmp_eq0000> created at line 95.
    Found 5-bit comparator equal for signal <dout2$cmp_eq0000> created at line 96.
    Summary:
        inferred   2 Comparator(s).
Unit <regfile> synthesized.


Synthesizing Unit <alu>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/alu.vhd".
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
    Found 32-bit register for signal <s>.
    Found 32-bit addsub for signal <s$addsub0000>.
    Found 32-bit comparator less for signal <s$cmp_lt0000> created at line 102.
    Found 32-bit comparator less for signal <s$cmp_lt0001> created at line 108.
    Found 32-bit xor2 for signal <s$xor0000> created at line 98.
    Summary:
        inferred  32 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   2 Comparator(s).
Unit <alu> synthesized.


Synthesizing Unit <sc_uart>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/sc_uart.vhd".
WARNING:Xst:647 - Input <wr_data<31:8>> is never used.
WARNING:Xst:646 - Signal <tf_half> is assigned but never used.
    Found finite state machine <FSM_0> for signal <uart_rx_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | s0                                             |
    | Power Up State     | s0                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 1-bit latch for signal <rd_data_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <rd_data_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <rd_data_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <rd_data_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <rd_data_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <rd_data_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <rd_data_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <rd_data_7>.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
    Found 8x1-bit ROM for signal <rx_d>.
    Found 32-bit up counter for signal <clk16>.
    Found 4-bit up counter for signal <clkrx>.
    Found 4-bit up counter for signal <clktx>.
    Found 4-bit up counter for signal <i>.
    Found 4-bit register for signal <i0>.
    Found 3-bit register for signal <ncts_buf>.
    Found 1-bit register for signal <rf_wr>.
    Found 10-bit register for signal <rsr>.
    Found 3-bit register for signal <rx_buf>.
    Found 1-bit register for signal <rx_clk>.
    Found 4-bit adder for signal <rx_clk$addsub0000> created at line 206.
    Found 1-bit register for signal <rx_clk_ena>.
    Found 3-bit register for signal <rxd_reg>.
    Found 1-bit register for signal <tf_rd>.
    Found 10-bit register for signal <tsr>.
    Found 1-bit register for signal <tx_clk>.
    Found 4-bit adder for signal <tx_clk$addsub0000> created at line 196.
    Found 4-bit adder for signal <uart_rx_state$add0000> created at line 344.
    Found 1-bit register for signal <uart_tx_state<0>>.
    Found 4-bit adder for signal <uart_tx_state_0$addsub0000> created at line 272.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred   1 ROM(s).
        inferred   4 Counter(s).
        inferred  39 D-type flip-flop(s).
        inferred   4 Adder/Subtractor(s).
Unit <sc_uart> synthesized.


Synthesizing Unit <decode>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd".
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
    Found 1-bit register for signal <fwop1>.
    Found 1-bit register for signal <fwop2>.
    Found 1-bit register for signal <fw_pc>.
    Found 16-bit register for signal <big_op>.
    Found 1-bit register for signal <fwshiftop>.
    Found 3-bit register for signal <brzero>.
    Found 32-bit register for signal <newpc>.
    Found 4-bit comparator equal for signal <fwop1$cmp_eq0000> created at line 165.
    Found 4-bit comparator equal for signal <fwop2$cmp_eq0000> created at line 168.
    Found 4-bit comparator equal for signal <fwop2$cmp_eq0001> created at line 247.
    Found 4-bit comparator equal for signal <fwshiftop$cmp_eq0000> created at line 209.
    Found 4-bit register for signal <lastdest>.
    Found 32-bit adder for signal <newpc$addsub0000> created at line 236.
    Found 1-bit xor2 for signal <reg2full_3$xor0000> created at line 126.
    Found 32-bit register for signal <sop1>.
    Found 32-bit register for signal <sop2>.
    Summary:
        inferred 123 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   4 Comparator(s).
Unit <decode> synthesized.


Synthesizing Unit <execute>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd".
WARNING:Xst:647 - Input <big_op<15>> is never used.
    Found 4-bit register for signal <regaddr>.
    Found 32-bit 4-to-1 multiplexer for signal <selected_r>.
    Found 1-bit register for signal <wasext>.
    Found 1-bit register for signal <wasmem>.
    Summary:
        inferred   6 D-type flip-flop(s).
        inferred  32 Multiplexer(s).
Unit <execute> synthesized.


Synthesizing Unit <cpu>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/cpu.vhd".
Unit <cpu> synthesized.


Synthesizing Unit <mysio>.
    Related source file is "/home/andi/xilinx/diogenes/vhdl/sio.vhd".
WARNING:Xst:646 - Signal <extaddr<13>> is assigned but never used.
WARNING:Xst:646 - Signal <urd_data<31:16>> is assigned but never used.
WARNING:Xst:737 - Found 16-bit latch for signal <extdin>.
    Found 4-bit register for signal <lcd_d_l>.
    Found 1-bit register for signal <lcd_e_l>.
    Found 1-bit register for signal <lcd_rs_l>.
    Found 1-bit register for signal <lcd_rw_l>.
    Found 10-bit register for signal <pmem_addr_m>.
    Found 16-bit register for signal <pmem_din_m>.
    Found 1-bit register for signal <pmem_we_m>.
    Found 8-bit register for signal <test_led>.
    Found 13-bit register for signal <vmem_addr_m>.
    Found 8-bit register for signal <vmem_din_m>.
    Found 1-bit register for signal <vmem_we_m>.
    Found 1-bit register for signal <was_button>.
    Found 1-bit register for signal <was_uart>.
    Summary:
        inferred  66 D-type flip-flop(s).
Unit <mysio> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 8x1-bit ROM                                           : 1
# Adders/Subtractors                                   : 9
 10-bit adder                                          : 3
 32-bit adder                                          : 1
 32-bit addsub                                         : 1
 4-bit adder                                           : 4
# Counters                                             : 6
 10-bit up counter                                     : 2
 32-bit up counter                                     : 1
 4-bit up counter                                      : 3
# Registers                                            : 152
 1-bit register                                        : 133
 10-bit register                                       : 1
 13-bit register                                       : 2
 16-bit register                                       : 2
 3-bit register                                        : 1
 32-bit register                                       : 3
 4-bit register                                        : 5
 8-bit register                                        : 5
# Latches                                              : 9
 1-bit latch                                           : 8
 16-bit latch                                          : 1
# Comparators                                          : 14
 10-bit comparator greater                             : 2
 10-bit comparator less                                : 4
 32-bit comparator less                                : 2
 4-bit comparator equal                                : 4
 5-bit comparator equal                                : 2
# Multiplexers                                         : 4
 32-bit 4-to-1 multiplexer                             : 4
# Logic shifters                                       : 2
 32-bit shifter logical left                           : 1
 32-bit shifter logical right                          : 1
# Xors                                                 : 2
 1-bit xor2                                            : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <sc_uartc/uart_rx_state> on signal <uart_rx_state[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 s0    | 00
 s1    | 01
 s2    | 10
-------------------
Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/Xilinx92.
Reading core <video_ram.ngc>.
Loading core <video_ram> for timing and area information for instance <video_ram_c>.
WARNING:Xst:2404 -  FFs/Latches <big_op<15:15>> (without init value) have a constant value of 0 in block <decode>.
WARNING:Xst:2404 -  FFs/Latches <brzero<2:2>> (without init value) have a constant value of 0 in block <decode>.
WARNING:Xst:2677 - Node <pixel_buf_3> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <pixel_buf_4> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <pixel_buf_5> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <pixel_buf_6> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <pixel_buf_7> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <pixel_3> of sequential type is unconnected in block <vga>.
WARNING:Xst:1710 - FF/Latch  <big_op_9> (without init value) has a constant value of 0 in block <decode>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <big_op_10> (without init value) has a constant value of 0 in block <decode>.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <8>.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <9>.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <10>.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <11>.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <12>.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <13>.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <14>.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <15>.
WARNING:Xst:2677 - Node <rd_prev> of sequential type is unconnected in block <g1[0].f1>.
WARNING:Xst:2677 - Node <rd_prev> of sequential type is unconnected in block <g1[0].f1>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# ROMs                                                 : 1
 8x1-bit ROM                                           : 1
# Adders/Subtractors                                   : 9
 10-bit adder                                          : 2
 3-bit adder                                           : 1
 32-bit adder                                          : 1
 32-bit addsub                                         : 1
 4-bit adder                                           : 4
# Counters                                             : 6
 10-bit up counter                                     : 2
 32-bit up counter                                     : 1
 4-bit up counter                                      : 3
# Registers                                            : 352
 Flip-Flops                                            : 352
# Latches                                              : 9
 1-bit latch                                           : 8
 16-bit latch                                          : 1
# Comparators                                          : 14
 10-bit comparator greater                             : 2
 10-bit comparator less                                : 4
 32-bit comparator less                                : 2
 4-bit comparator equal                                : 4
 5-bit comparator equal                                : 2
# Multiplexers                                         : 4
 32-bit 4-to-1 multiplexer                             : 4
# Logic shifters                                       : 2
 32-bit shifter logical left                           : 1
 32-bit shifter logical right                          : 1
# Xors                                                 : 2
 1-bit xor2                                            : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2677 - Node <cmp_rf/g1[0].f1/rd_prev> of sequential type is unconnected in block <sc_uart>.
WARNING:Xst:2677 - Node <cmp_tf/g1[0].f1/rd_prev> of sequential type is unconnected in block <sc_uart>.

Optimizing unit <mysio> ...

Optimizing unit <fetch> ...

Optimizing unit <barrel> ...

Optimizing unit <vga> ...

Optimizing unit <regfile> ...

Optimizing unit <alu> ...

Optimizing unit <decode> ...

Optimizing unit <sc_uart> ...

Optimizing unit <execute> ...
WARNING:Xst:1710 - FF/Latch  <extdin_8> (without init value) has a constant value of 0 in block <mysio>.
WARNING:Xst:1710 - FF/Latch  <extdin_9> (without init value) has a constant value of 0 in block <mysio>.
WARNING:Xst:1710 - FF/Latch  <extdin_10> (without init value) has a constant value of 0 in block <mysio>.
WARNING:Xst:1710 - FF/Latch  <extdin_11> (without init value) has a constant value of 0 in block <mysio>.
WARNING:Xst:1710 - FF/Latch  <extdin_12> (without init value) has a constant value of 0 in block <mysio>.
WARNING:Xst:1710 - FF/Latch  <extdin_13> (without init value) has a constant value of 0 in block <mysio>.
WARNING:Xst:1710 - FF/Latch  <extdin_14> (without init value) has a constant value of 0 in block <mysio>.
WARNING:Xst:1710 - FF/Latch  <extdin_15> (without init value) has a constant value of 0 in block <mysio>.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mysio, actual ratio is 15.
FlipFlop diogenes_cpu/pipestage1/first has been replicated 1 time(s)
FlipFlop diogenes_cpu/pipestage2/fwop1 has been replicated 1 time(s)
FlipFlop diogenes_cpu/pipestage2/fwop2 has been replicated 1 time(s)
FlipFlop diogenes_cpu/pipestage2/fwshiftop has been replicated 3 time(s)

Final Macro Processing ...

Processing Unit <mysio> :
        Found 3-bit shift register for signal <sc_uartc/rxd_reg_2>.
Unit <mysio> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 417
 Flip-Flops                                            : 417
# Shift Registers                                      : 1
 3-bit shift register                                  : 1

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : mysio.ngr
Top Level Output File Name         : mysio
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 35

Cell Usage :
# BELS                             : 1740
#      GND                         : 2
#      INV                         : 10
#      LUT1                        : 57
#      LUT2                        : 123
#      LUT2_D                      : 21
#      LUT2_L                      : 6
#      LUT3                        : 335
#      LUT3_D                      : 63
#      LUT3_L                      : 46
#      LUT4                        : 570
#      LUT4_D                      : 24
#      LUT4_L                      : 71
#      MUXCY                       : 200
#      MUXF5                       : 82
#      VCC                         : 2
#      XORCY                       : 128
# FlipFlops/Latches                : 434
#      FDC                         : 241
#      FDCE                        : 120
#      FDE                         : 36
#      FDP                         : 4
#      FDPE                        : 17
#      LD                          : 8
#      LDCP                        : 8
# RAMS                             : 4
#      RAMB16_S2_S2                : 4
# Shift Registers                  : 1
#      SRL16E                      : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 34
#      IBUF                        : 10
#      OBUF                        : 24
# Others                           : 4
#      dist_mem                    : 2
#      dmem                        : 1
#      pmem                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                     691  out of   4656    14%  
 Number of Slice Flip Flops:           434  out of   9312     4%  
 Number of 4 input LUTs:              1327  out of   9312    14%  
    Number used as logic:             1326
    Number used as Shift registers:      1
 Number of IOs:                         35
 Number of bonded IOBs:                 35  out of    232    15%  
 Number of BRAMs:                        4  out of     20    20%  
 Number of GCLKs:                        1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+-------------------------+-------+
Clock Signal                       | Clock buffer(FF name)   | Load  |
-----------------------------------+-------------------------+-------+
gclk                               | BUFGP                   | 423   |
was_button                         | NONE(extdin_0)          | 8     |
diogenes_cpu/pipestage2/big_op_13  | NONE(sc_uartc/rd_data_0)| 8     |
-----------------------------------+-------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------+----------------------------------------+-------+
Control Signal                                             | Buffer(FF name)                        | Load  |
-----------------------------------------------------------+----------------------------------------+-------+
diogenes_cpu/pipestage1/reset_inv(vga_c/reset_inv1_INV_0:O)| NONE(diogenes_cpu/pipestage3/regaddr_1)| 382   |
extdin_0__and0000(extdin_0__and00001:O)                    | NONE(extdin_0)                         | 1     |
extdin_0__and0001(extdin_0__and00011:O)                    | NONE(extdin_0)                         | 1     |
extdin_4__and0000(extdin_4__and00001:O)                    | NONE(extdin_4)                         | 1     |
extdin_4__and0001(extdin_4__and00011:O)                    | NONE(extdin_4)                         | 1     |
extdin_7__and0000(extdin_7__and00001:O)                    | NONE(extdin_7)                         | 1     |
extdin_7__and0001(extdin_7__and00011:O)                    | NONE(extdin_7)                         | 1     |
extdin_2__and0000(extdin_2__and00001:O)                    | NONE(extdin_2)                         | 1     |
extdin_2__and0001(extdin_2__and00011:O)                    | NONE(extdin_2)                         | 1     |
extdin_6__and0000(extdin_6__and00001:O)                    | NONE(extdin_6)                         | 1     |
extdin_6__and0001(extdin_6__and00011:O)                    | NONE(extdin_6)                         | 1     |
extdin_1__and0000(extdin_1__and00001:O)                    | NONE(extdin_1)                         | 1     |
extdin_1__and0001(extdin_1__and00011:O)                    | NONE(extdin_1)                         | 1     |
extdin_3__and0000(extdin_3__and00001:O)                    | NONE(extdin_3)                         | 1     |
extdin_3__and0001(extdin_3__and00011:O)                    | NONE(extdin_3)                         | 1     |
extdin_5__and0000(extdin_5__and00001:O)                    | NONE(extdin_5)                         | 1     |
extdin_5__and0001(extdin_5__and00011:O)                    | NONE(extdin_5)                         | 1     |
-----------------------------------------------------------+----------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.634ns (Maximum Frequency: 94.038MHz)
   Minimum input arrival time before clock: 10.390ns
   Maximum output required time after clock: 9.033ns
   Maximum combinational path delay: 5.432ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'gclk'
  Clock period: 10.634ns (frequency: 94.038MHz)
  Total number of paths / destination ports: 51871 / 697
-------------------------------------------------------------------------
Delay:               10.634ns (Levels of Logic = 16)
  Source:            diogenes_cpu/pipestage2/sop1_23 (FF)
  Destination:       diogenes_cpu/pipestage1/curpc_9 (FF)
  Source Clock:      gclk rising
  Destination Clock: gclk rising

  Data Path: diogenes_cpu/pipestage2/sop1_23 to diogenes_cpu/pipestage1/curpc_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.591   0.622  diogenes_cpu/pipestage2/sop1_23 (diogenes_cpu/pipestage2/sop1_23)
     LUT4:I0->O            1   0.704   0.499  diogenes_cpu/pipestage1/cpc_cmp_eq0002269 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map94)
     LUT2:I1->O            1   0.704   0.455  diogenes_cpu/pipestage1/cpc_cmp_eq0002270 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map95)
     LUT4:I2->O            5   0.704   0.637  diogenes_cpu/pipestage1/cpc_cmp_eq0002387 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map128)
     LUT4:I3->O           18   0.704   1.103  diogenes_cpu/pipestage1/cpc_or00001 (diogenes_cpu/pipestage1/cpc_or0000)
     LUT4_D:I2->O          1   0.704   0.455  diogenes_cpu/pipestage1/Mmux_cpc118 (diogenes_cpu/pipestage1/Mmux_cpc1_map7)
     LUT4:I2->O            2   0.704   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_lut<0> (diogenes_cpu/pipestage1/N4)
     MUXCY:S->O            1   0.464   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<0> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<1> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<2> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<3> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<3>)
     MUXCY:CI->O           1   0.059   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<4> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<4>)
     MUXCY:CI->O           1   0.059   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<5> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<6> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<6>)
     MUXCY:CI->O           1   0.059   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<7> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<7>)
     MUXCY:CI->O           0   0.059   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<8> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<8>)
     XORCY:CI->O           1   0.804   0.000  diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_xor<9> (diogenes_cpu/pipestage1/curpc_9_0_add0000<9>)
     FDC:D                     0.308          diogenes_cpu/pipestage1/curpc_9
    ----------------------------------------
    Total                     10.634ns (6.863ns logic, 3.771ns route)
                                       (64.5% logic, 35.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk'
  Total number of paths / destination ports: 7219 / 162
-------------------------------------------------------------------------
Offset:              10.390ns (Levels of Logic = 7)
  Source:            pmemc:douta<14> (PAD)
  Destination:       diogenes_cpu/pipestage2/sop2_30 (FF)
  Destination Clock: gclk rising

  Data Path: pmemc:douta<14> to diogenes_cpu/pipestage2/sop2_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    pmem:douta<14>        14   0.000   1.175  pmemc (mem_dout_cpu<14>)
     LUT3:I0->O           14   0.704   1.004  diogenes_cpu/pipestage2/big_op_mux0010<12>11 (diogenes_cpu/pipestage2/N201)
     LUT4:I3->O            3   0.704   0.610  diogenes_cpu/pipestage2/reg2full_0_mux000111 (diogenes_cpu/pipestage2/N2)
     LUT4:I1->O            2   0.704   0.482  diogenes_cpu/pipestage2/reg2full_0_mux00012 (diogenes_cpu/pipestage2/reg2full<0>)
     LUT4_D:I2->LO         1   0.704   0.104  diogenes_cpu/pipestage2/rf/dout2_cmp_eq0000553 (N4520)
     LUT4:I3->O           32   0.704   1.297  diogenes_cpu/pipestage2/rf/dout2_cmp_eq0000555_1 (diogenes_cpu/pipestage2/rf/dout2_cmp_eq0000555)
     LUT3_D:I2->O          2   0.704   0.482  diogenes_cpu/pipestage2/rf/dout2<9>1 (diogenes_cpu/pipestage2/rout2<9>)
     LUT4:I2->O            1   0.704   0.000  diogenes_cpu/pipestage2/sop2_17_mux00041 (diogenes_cpu/pipestage2/sop2_17_mux0004)
     FDC:D                     0.308          diogenes_cpu/pipestage2/sop2_17
    ----------------------------------------
    Total                     10.390ns (5.236ns logic, 5.154ns route)
                                       (50.4% logic, 49.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'was_button'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              2.729ns (Levels of Logic = 2)
  Source:            button<0> (PAD)
  Destination:       extdin_0 (LATCH)
  Destination Clock: was_button falling

  Data Path: button<0> to extdin_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.218   0.499  button_0_IBUF (button_0_IBUF)
     LUT3:I1->O            1   0.704   0.000  extdin_mux0001<0>1 (extdin_mux0001<0>)
     LDCP:D                    0.308          extdin_0
    ----------------------------------------
    Total                      2.729ns (2.230ns logic, 0.499ns route)
                                       (81.7% logic, 18.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk'
  Total number of paths / destination ports: 2542 / 181
-------------------------------------------------------------------------
Offset:              9.033ns (Levels of Logic = 6)
  Source:            diogenes_cpu/pipestage2/sop1_23 (FF)
  Destination:       pmemc:addra<9> (PAD)
  Source Clock:      gclk rising

  Data Path: diogenes_cpu/pipestage2/sop1_23 to pmemc:addra<9>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.591   0.622  diogenes_cpu/pipestage2/sop1_23 (diogenes_cpu/pipestage2/sop1_23)
     LUT4:I0->O            1   0.704   0.499  diogenes_cpu/pipestage1/cpc_cmp_eq0002269 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map94)
     LUT2:I1->O            1   0.704   0.455  diogenes_cpu/pipestage1/cpc_cmp_eq0002270 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map95)
     LUT4:I2->O            5   0.704   0.637  diogenes_cpu/pipestage1/cpc_cmp_eq0002387 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map128)
     LUT4:I3->O           18   0.704   1.103  diogenes_cpu/pipestage1/cpc_or00001 (diogenes_cpu/pipestage1/cpc_or0000)
     LUT4:I2->O            2   0.704   0.482  diogenes_cpu/pipestage1/Mmux_cpc3222 (diogenes_cpu/pipestage1/Mmux_cpc32_map9)
     LUT4:I2->O            1   0.704   0.420  diogenes_cpu/pipestage1/Mmux_cpc3228 (mem_addr_cpu<9>)
    pmem:addra<9>              0.000          pmemc
    ----------------------------------------
    Total                      9.033ns (4.815ns logic, 4.218ns route)
                                       (53.3% logic, 46.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'was_button'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              2.366ns (Levels of Logic = 1)
  Source:            extdin_7 (LATCH)
  Destination:       diogenes_cpu/pipestage2/rf/reg1:d<7> (PAD)
  Source Clock:      was_button falling

  Data Path: extdin_7 to diogenes_cpu/pipestage2/rf/reg1:d<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP:G->Q             1   0.676   0.455  extdin_7 (extdin_7)
     LUT3:I2->O            3   0.704   0.531  diogenes_cpu/pipestage3/Mmux_selected_r30 (diogenes_cpu/result<7>)
    dist_mem:d<7>              0.000          diogenes_cpu/pipestage2/rf/reg1
    ----------------------------------------
    Total                      2.366ns (1.380ns logic, 0.986ns route)
                                       (58.3% logic, 41.7% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 140 / 77
-------------------------------------------------------------------------
Delay:               5.432ns (Levels of Logic = 3)
  Source:            pmemc:douta<14> (PAD)
  Destination:       diogenes_cpu/pipestage2/rf/reg2:dpra<1> (PAD)

  Data Path: pmemc:douta<14> to diogenes_cpu/pipestage2/rf/reg2:dpra<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    pmem:douta<14>        14   0.000   1.175  pmemc (mem_dout_cpu<14>)
     LUT3:I0->O           14   0.704   1.004  diogenes_cpu/pipestage2/big_op_mux0010<12>11 (diogenes_cpu/pipestage2/N201)
     LUT4:I3->O            3   0.704   0.610  diogenes_cpu/pipestage2/reg2full_0_mux000111 (diogenes_cpu/pipestage2/N2)
     LUT4:I1->O            3   0.704   0.531  diogenes_cpu/pipestage2/reg2full_1_mux00011 (diogenes_cpu/pipestage2/reg2full<1>)
    dist_mem:dpra<1>           0.000          diogenes_cpu/pipestage2/rf/reg2
    ----------------------------------------
    Total                      5.432ns (2.112ns logic, 3.320ns route)
                                       (38.9% logic, 61.1% route)

=========================================================================
CPU : 44.92 / 44.99 s | Elapsed : 45.00 / 45.00 s
 
--> 


Total memory usage is 159876 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   63 (   0 filtered)
Number of infos    :   25 (   0 filtered)