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https://opencores.org/ocsvn/diogenes/diogenes/trunk
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[/] [diogenes/] [tags/] [initial/] [vhdl/] [mysio_isim_beh.wfs] - Rev 236
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version 3
0
CLOCK_LIST_BEGIN
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
/mysio/gclk
/mysio/reset
/mysio/simulation
/mysio/rx
/mysio/tx
/mysio/test
/mysio/nreset
/mysio/wr_gen
/mysio/rd_gen
/mysio/rd_data
/mysio/wr_data
/mysio/addr
/mysio/mem_addr
/mysio/mem_dout
/mysio/mem_hi
/mysio/pmem_addr
/mysio/pmem_din
/mysio/pmem_dout
/mysio/pmem_we
/mysio/pmem_clk
/mysio/testout
/mysio/clk_cpu
/mysio/count
/mysio/extaddr
/mysio/extdin
/mysio/extdout
/mysio/extwr
/mysio/extrd
/mysio/mem_addr_cpu
/mysio/mem_dout_cpu
/mysio/reset_cpu
/mysio/cpu_running
/mysio/state
/mysio/mode
SIGNAL_ORDER_END
DIFFERENTIAL_CLKS_BEGIN
DIFFERENTIAL_CLKS_END
DIVIDERS_BEGIN
DIVIDERS_END
SIGPROPS_BEGIN
/mysio/gclk
2
0
/mysio/reset
2
0
/mysio/simulation
2
0
/mysio/rx
2
0
/mysio/tx
2
0
/mysio/test
2
0
/mysio/nreset
2
0
/mysio/wr_gen
2
0
/mysio/rd_gen
2
0
/mysio/rd_data
2
0
/mysio/wr_data
2
0
/mysio/addr
2
0
/mysio/mem_addr
2
0
/mysio/mem_dout
2
0
/mysio/mem_hi
2
0
/mysio/pmem_addr
2
0
/mysio/pmem_din
2
0
/mysio/pmem_dout
2
0
/mysio/pmem_we
2
0
/mysio/pmem_clk
2
0
/mysio/testout
2
0
/mysio/clk_cpu
2
0
/mysio/count
2
0
/mysio/extaddr
2
0
/mysio/extdin
2
0
/mysio/extdout
2
0
/mysio/extwr
2
0
/mysio/extrd
2
0
/mysio/mem_addr_cpu
2
0
/mysio/mem_dout_cpu
2
0
/mysio/reset_cpu
2
0
/mysio/cpu_running
2
0
/mysio/state
2
0
/mysio/mode
2
0
SIGPROPS_END