Subversion Repositories diogenes

Release 9.2i Map J.36
Xilinx Map Application Log File for Design 'mysio'

Design Information
------------------
Command Line   : map -ise /home/andi/xilinx/diogenes/vhdl/rs232.ise -intstyle
ise -p xc3s500e-fg320-4 -cm area -pr b -k 4 -c 100 -o mysio_map.ncd mysio.ngd
mysio.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.1.1.1 $
Mapped Date    : Mon Jan 28 21:05:16 2008

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    4
Logic Utilization:
  Total Number Slice Registers:       413 out of   9,312    4%
    Number used as Flip Flops:                   397
    Number used as Latches:                       16
  Number of 4 input LUTs:           1,263 out of   9,312   13%
Logic Distribution:
  Number of occupied Slices:                          784 out of   4,656   16%
    Number of Slices containing only related logic:     784 out of     784  100%
    Number of Slices containing unrelated logic:          0 out of     784    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          1,449 out of   9,312   15%
  Number used as logic:              1,263
  Number used as a route-thru:          57
  Number used for Dual Port RAMs:      128
    (Two LUTs used per Dual Port RAM)
  Number used as Shift registers:        1
  Number of bonded IOBs:               35 out of     232   15%
    IOB Flip Flops:                    21
  Number of Block RAMs:                7 out of      20   35%
  Number of GCLKs:                     1 out of      24    4%

Total equivalent gate count for design:  479,243
Additional JTAG gate count for IOBs:  1,680
Peak Memory Usage:  153 MB
Total REAL time to MAP completion:  6 secs 
Total CPU time to MAP completion:   6 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "mysio_map.mrp" for details.