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Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.06 s | Elapsed : 0.00 / 0.00 s
 
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/andi/xilinx/rs232/fifo.vhd" in Library work.
Architecture rtl of Entity fifo_elem is up to date.
Architecture rtl of Entity fifo is up to date.
Compiling vhdl file "/home/andi/xilinx/rs232/sc_uart.vhd" in Library work.
Architecture rtl of Entity sc_uart is up to date.
CPU : 0.04 / 0.10 s | Elapsed : 0.00 / 0.00 s
 
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Total memory usage is 91096 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)