Subversion Repositories diogenes

--------------------------------------------------------------------------------
Release 9.2i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

trce -ise /home/andi/xilinx/rs232/rs232.ise -intstyle ise -e 3 -s 5 -xml sio
sio.ncd -o sio.twr sio.pcf -ucf sio.ucf

Design file:              sio.ncd
Physical constraint file: sio.pcf
Device,package,speed:     xc3s500e,fg320,-5 (PRODUCTION 1.26 2007-04-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: NET "clk_BUFGP/IBUFG" PERIOD = 25 ns HIGH 50%;

 3094 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   6.618ns.
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.618|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 3094 paths, 0 nets, and 842 connections

Design statistics:
   Minimum period:   6.618ns   (Maximum frequency: 151.103MHz)


Analysis completed Tue Nov 13 12:06:05 2007 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 92 MB