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##############################################################
#
# Xilinx Core Generator version J.36
# Date: Mon Jan 28 19:09:12 2008
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Dual_Port_Block_Memory family Xilinx,_Inc. 6.3
# END Select
# BEGIN Parameters
CSET coefficient_file=/home/andi/xilinx/rs232/vga/video_ram.coe
CSET component_name=video_ram
CSET configuration_port_a=Read_Only
CSET configuration_port_b=Write_Only
CSET depth_a=8192
CSET depth_b=8192
CSET disable_warning_messages=true
CSET global_init_value=0
CSET load_init_file=true
CSET port_a_active_clock_edge=Rising_Edge_Triggered
CSET port_a_additional_output_pipe_stages=0
CSET port_a_enable_pin=false
CSET port_a_enable_pin_polarity=Active_High
CSET port_a_handshaking_pins=false
CSET port_a_init_pin=false
CSET port_a_init_value=0
CSET port_a_initialization_pin_polarity=Active_High
CSET port_a_register_inputs=false
CSET port_a_write_enable_polarity=Active_High
CSET port_b_active_clock_edge=Rising_Edge_Triggered
CSET port_b_additional_output_pipe_stages=0
CSET port_b_enable_pin=false
CSET port_b_enable_pin_polarity=Active_High
CSET port_b_handshaking_pins=false
CSET port_b_init_pin=false
CSET port_b_init_value=0
CSET port_b_initialization_pin_polarity=Active_High
CSET port_b_register_inputs=false
CSET port_b_write_enable_polarity=Active_High
CSET primitive_selection=Optimize_For_Area
CSET select_primitive=16kx1
CSET width_a=8
CSET width_b=8
CSET write_mode_port_a=Read_After_Write
CSET write_mode_port_b=Read_After_Write
# END Parameters
GENERATE
# CRC:   abce57