URL
https://opencores.org/ocsvn/diogenes/diogenes/trunk
Subversion Repositories diogenes
[/] [diogenes/] [tags/] [initial/] [vhdl/] [xst/] [work/] [hdpdeps.ref] - Rev 236
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V3 98FL /home/andi/xilinx/diogenes/rs232/cpu/alu.vhd 2007/11/23.11:10:38 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/barrel.vhd 2007/11/22.12:36:20 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/cpu.vhd 2007/11/23.12:01:14 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/decode.vhd 2007/11/23.11:24:22 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/dist_mem.vhd 2007/02/19.22:15:40 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/dmem.vhd 2007/11/21.15:18:40 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/execute.vhd 2007/11/23.12:00:38 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/fetch.vhd 2007/11/22.20:09:28 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/pmem.vhd 2007/11/23.11:40:30 J.36FL /home/andi/xilinx/diogenes/rs232/cpu/regfile.vhd 2007/04/02.07:53:40 J.36FL /home/andi/xilinx/diogenes/rs232/fifo.vhd 2007/11/09.18:26:10 J.36FL /home/andi/xilinx/diogenes/rs232/sc_uart.vhd 2007/11/26.19:06:42 J.36FL /home/andi/xilinx/diogenes/rs232/sio.vhd 2008/01/14.13:59:21 J.36FL /home/andi/xilinx/diogenes/rs232/types.vhd 2007/11/13.19:16:54 J.36FL /home/andi/xilinx/diogenes/vhdl/cpu/alu.vhd 2008/01/16.20:01:36 J.36EN work/alu 1201550666 FL /home/andi/xilinx/diogenes/vhdl/cpu/alu.vhd \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583 PB work/types 1201550659AR work/alu/Behavioral 1201550667 \FL /home/andi/xilinx/diogenes/vhdl/cpu/alu.vhd EN work/alu 1201550666 \CP barrelFL /home/andi/xilinx/diogenes/vhdl/cpu/barrel.vhd 2008/01/16.20:01:35 J.36EN work/barrel 1201550660 FL /home/andi/xilinx/diogenes/vhdl/cpu/barrel.vhd \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583AR work/barrel/Behavioral 1201550661 \FL /home/andi/xilinx/diogenes/vhdl/cpu/barrel.vhd EN work/barrel 1201550660FL /home/andi/xilinx/diogenes/vhdl/cpu/cpu.vhd 2008/01/18.15:51:11 J.36EN work/cpu 1201550688 FL /home/andi/xilinx/diogenes/vhdl/cpu/cpu.vhd \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583 PB work/types 1201550659 LB UNISIM \PH unisim/VCOMPONENTS 1177545586AR work/cpu/Behavioral 1201550689 \FL /home/andi/xilinx/diogenes/vhdl/cpu/cpu.vhd EN work/cpu 1201550688 \CP fetch CP decode CP executeFL /home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd 2008/01/16.20:01:36 J.36EN work/decode 1201550672 FL /home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583 PH ieee/NUMERIC_STD 1177545583 \PB work/types 1201550659AR work/decode/Behavioral 1201550673 \FL /home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd EN work/decode 1201550672 \CP regfileFL /home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.vhd 2008/01/16.20:01:36 J.36EN work/dist_mem 1201550662 FL /home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.vhd \PB ieee/std_logic_1164 1177545575AR work/dist_mem/dist_mem_a 1201550663 \FL /home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.vhd EN work/dist_mem 1201550662FL /home/andi/xilinx/diogenes/vhdl/cpu/dmem.vhd 2008/01/16.20:01:35 J.36EN work/dmem 1201550664 FL /home/andi/xilinx/diogenes/vhdl/cpu/dmem.vhd \PB ieee/std_logic_1164 1177545575AR work/dmem/dmem_a 1201550665 \FL /home/andi/xilinx/diogenes/vhdl/cpu/dmem.vhd EN work/dmem 1201550664FL /home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd 2008/01/18.15:59:34 J.36EN work/execute 1201550674 FL /home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583 PB work/types 1201550659 LB UNISIM \PH unisim/VCOMPONENTS 1177545586AR work/execute/Behavioral 1201550675 \FL /home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd EN work/execute 1201550674 \CP dmem CP aluFL /home/andi/xilinx/diogenes/vhdl/cpu/fetch.vhd 2008/01/16.20:01:35 J.36EN work/fetch 1201550670 FL /home/andi/xilinx/diogenes/vhdl/cpu/fetch.vhd \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583 PH ieee/NUMERIC_STD 1177545583 \PB work/types 1201550659AR work/fetch/Behavioral 1201550671 \FL /home/andi/xilinx/diogenes/vhdl/cpu/fetch.vhd EN work/fetch 1201550670FL /home/andi/xilinx/diogenes/vhdl/cpu/pmem.vhd 2008/01/16.20:01:35 J.36EN work/pmem 1201550686 FL /home/andi/xilinx/diogenes/vhdl/cpu/pmem.vhd \PB ieee/std_logic_1164 1177545575AR work/pmem/pmem_a 1201550687 \FL /home/andi/xilinx/diogenes/vhdl/cpu/pmem.vhd EN work/pmem 1201550686FL /home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd 2008/01/16.20:01:36 J.36EN work/regfile 1201550668 FL /home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583 PB work/types 1201550659AR work/regfile/Behavioral 1201550669 \FL /home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd EN work/regfile 1201550668 \CP dist_memFL /home/andi/xilinx/diogenes/vhdl/fifo.vhd 2008/01/16.20:01:34 J.36EN work/fifo_elem 1201550676 FL /home/andi/xilinx/diogenes/vhdl/fifo.vhd \PB ieee/std_logic_1164 1177545575AR work/fifo_elem/rtl 1201550677 \FL /home/andi/xilinx/diogenes/vhdl/fifo.vhd EN work/fifo_elem 1201550676EN work/fifo 1201550678 \FL /home/andi/xilinx/diogenes/vhdl/fifo.vhd PB ieee/std_logic_1164 1177545575AR work/fifo/rtl 1201550679 \FL /home/andi/xilinx/diogenes/vhdl/fifo.vhd EN work/fifo 1201550678 \CP fifo_elemFL /home/andi/xilinx/diogenes/vhdl/sc_uart.vhd 2008/01/16.20:01:34 J.36EN work/sc_uart 1201550684 FL /home/andi/xilinx/diogenes/vhdl/sc_uart.vhd \PB ieee/std_logic_1164 1177545575 PH ieee/NUMERIC_STD 1177545583AR work/sc_uart/rtl 1201550685 \FL /home/andi/xilinx/diogenes/vhdl/sc_uart.vhd EN work/sc_uart 1201550684 \CP fifoFL /home/andi/xilinx/diogenes/vhdl/sio.vhd 2008/01/24.12:14:18 J.36EN work/mysio 1201550690 FL /home/andi/xilinx/diogenes/vhdl/sio.vhd \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583 LB UNISIM PH unisim/VCOMPONENTS 1177545586 \PB work/types 1201550659AR work/mysio/Behavioral 1201550691 \FL /home/andi/xilinx/diogenes/vhdl/sio.vhd EN work/mysio 1201550690 CP vga \CP sc_uart CP pmem CP cpuFL /home/andi/xilinx/diogenes/vhdl/types.vhd 2008/01/16.20:01:33 J.36PH work/types 1201550658 FL /home/andi/xilinx/diogenes/vhdl/types.vhd \PB ieee/std_logic_1164 1177545575PB work/types 1201550659 \FL /home/andi/xilinx/diogenes/vhdl/types.vhd PH work/types 1201550658FL /home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl 2008/01/19.14:04:44 J.36EN work/vga 1201550682 FL /home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl \PB ieee/std_logic_1164 1177545575 PB ieee/std_logic_arith 1177545576 \PB ieee/STD_LOGIC_UNSIGNED 1177545583AR work/vga/Behavioral 1201550683 \FL /home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl EN work/vga 1201550682 \CP video_ramFL /home/andi/xilinx/diogenes/vhdl/video_ram.vhd 2008/01/28.20:10:03 J.36EN work/video_ram 1201550680 FL /home/andi/xilinx/diogenes/vhdl/video_ram.vhd \PB ieee/std_logic_1164 1177545575AR work/video_ram/video_ram_a 1201550681 \FL /home/andi/xilinx/diogenes/vhdl/video_ram.vhd EN work/video_ram 1201550680FL /home/andi/xilinx/rs232/cpu/alu.vhd 2008/01/16.20:01:36 J.36FL /home/andi/xilinx/rs232/cpu/barrel.vhd 2008/01/16.20:01:35 J.36FL /home/andi/xilinx/rs232/cpu/cpu.vhd 2008/01/18.15:51:11 J.36FL /home/andi/xilinx/rs232/cpu/decode.vhd 2008/01/16.20:01:36 J.36FL /home/andi/xilinx/rs232/cpu/dist_mem.vhd 2008/01/16.20:01:36 J.36FL /home/andi/xilinx/rs232/cpu/dmem.vhd 2008/01/16.20:01:35 J.36FL /home/andi/xilinx/rs232/cpu/execute.vhd 2008/01/18.15:59:34 J.36FL /home/andi/xilinx/rs232/cpu/fetch.vhd 2008/01/16.20:01:35 J.36FL /home/andi/xilinx/rs232/cpu/pmem.vhd 2008/01/16.20:01:35 J.36FL /home/andi/xilinx/rs232/cpu/regfile.vhd 2008/01/16.20:01:36 J.36FL /home/andi/xilinx/rs232/fifo.vhd 2008/01/16.20:01:34 J.36FL /home/andi/xilinx/rs232/sc_uart.vhd 2008/01/16.20:01:34 J.36FL /home/andi/xilinx/rs232/sio.vhd 2008/01/24.12:14:18 J.36FL /home/andi/xilinx/rs232/types.vhd 2008/01/16.20:01:33 J.36FL /home/andi/xilinx/rs232/vga.vhdl 2008/01/16.12:56:44 J.36FL /home/andi/xilinx/rs232/vga/coregen/video_ram.vhd 2008/01/19.13:47:47 J.36FL /home/andi/xilinx/rs232/vga/vga.vhdl 2008/01/19.14:04:44 J.36FL /home/andi/xilinx/rs232/video_ram.vhd 2008/01/28.20:10:03 J.36