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[/] [diogenes/] [trunk/] [vhdl/] [cpu/] [_xmsgs/] [map.xmsgs] - Rev 236
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<?xml version="1.0" encoding="UTF-8"?><!-- IMPORTANT: This is an internal file that has been generatedby the Xilinx ISE software. Any direct editing orchanges made to this file may result in unpredictablebehavior or data corruption. It is strongly advised thatusers do not edit the contents of this file. --><messages><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">extdata_7_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">extdata<7></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu/pipestage3</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pipestage3/extdata_7_OBUF</arg>'.</msg><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">extdata_6_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">extdata<6></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu/pipestage3</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pipestage3/extdata_6_OBUF</arg>'.</msg><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">extdata_5_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">extdata<5></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu/pipestage3</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pipestage3/extdata_5_OBUF</arg>'.</msg><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">extdata_4_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">extdata<4></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu/pipestage3</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pipestage3/extdata_4_OBUF</arg>'.</msg><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">extdata_3_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">extdata<3></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu/pipestage3</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pipestage3/extdata_3_OBUF</arg>'.</msg><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">extdata_2_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">extdata<2></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu/pipestage3</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pipestage3/extdata_2_OBUF</arg>'.</msg><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">extdata_1_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">extdata<1></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu/pipestage3</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pipestage3/extdata_1_OBUF</arg>'.</msg><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">extdata_0_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">extdata<0></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu/pipestage3</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pipestage3/extdata_0_OBUF</arg>'.</msg><msg type="info" file="Map" num="110" delta="unknown" >output buffer '<arg fmt="%s" index="1">pcout_15_OBUF</arg>' driving design level port '<arg fmt="%s" index="2">pcout<15></arg>' is being pushed into module '<arg fmt="%s" index="3">ccpu</arg>' to enable I/O register usage. The buffer has been renamed as '<arg fmt="%s" index="4">ccpu/pcout_15_OBUF</arg>'.</msg><msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">N12</arg> has no load.</msg><msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">187</arg> more times for the following (max. 5 shown):<arg fmt="%s" index="4">N13,ccpu/newpc<31>,ccpu/newpc<30>,ccpu/newpc<29>,ccpu/newpc<28></arg>To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.</msg><msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.</msg><msg type="info" file="MapLib" num="863" delta="unknown" >The following Virtex BUFG(s) is/are being retargeted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:<arg fmt="%s" index="1">first symbol "first"</arg></msg><msg type="info" file="MapLib" num="159" delta="unknown" >Net Timing constraints on signal <arg fmt="%s" index="1">clk_in</arg> are pushed forward through input buffer.</msg><msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.</msg><msg type="warning" file="Pack" num="1237" delta="unknown" >The register <arg fmt="%s" index="1">ccpu/pipestage2/big_op_10</arg> failed to join the output side of an I/O component. <arg fmt="%z" index="2">Symbol ccpu/pipestage2/big_op_10 is not under the same hierarchy region as symbol exten_OBUF. There are three ways to fix the problem:1. Put both symbols under the same hierarchy region and process the design. If the I/O buffer is being inferred by the synthesis tool, it is suggested to code I/O registers on the top level of code. If this can not be done, it is suggested to instantiate the proper I/O buffer in the lower level of code and disable I/O buffer inference for that port in the design.2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block ccpu/pipestage2 in the UCF file.3. Run map with the option -ignore_keep_hierarchy. This option will dissolve all hierarchy in the design.</arg></msg><msg type="warning" file="Pack" num="1237" delta="unknown" >The register <arg fmt="%s" index="1">ccpu/pipestage2/big_op_11</arg> failed to join the output side of an I/O component. <arg fmt="%z" index="2">Symbol ccpu/pipestage2/big_op_11 is not under the same hierarchy region as symbol extwe_OBUF. There are three ways to fix the problem:1. Put both symbols under the same hierarchy region and process the design. If the I/O buffer is being inferred by the synthesis tool, it is suggested to code I/O registers on the top level of code. If this can not be done, it is suggested to instantiate the proper I/O buffer in the lower level of code and disable I/O buffer inference for that port in the design.2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block ccpu/pipestage2 in the UCF file.3. Run map with the option -ignore_keep_hierarchy. This option will dissolve all hierarchy in the design.</arg></msg></messages>