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<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
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<messages>
<msg type="info" file="Place" num="834" delta="unknown" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">34</arg> IOs, <arg fmt="%d" index="2">8</arg> are locked and <arg fmt="%d" index="3">26</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg> 
</msg>

<msg type="warning" file="Route" num="455" delta="unknown" >CLK Net:<arg fmt="%s" index="1">extwe_OBUF</arg> may have excessive skew because 
   <arg fmt="%d" index="2">0</arg> CLK pins and <arg fmt="%d" index="3">1</arg> NON_CLK pins failed to route using a CLK template.
</msg>

</messages>