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The following files were generated for 'dist_mem' in directory 
L:\Xilinx91i\bin\nt\coregen\:

dist_mem.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

dist_mem.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

dist_mem_xmdf.tcl:
   Please see the core data sheet.

dist_mem_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

dist_mem.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

dist_mem_readme.txt:
   Text file indicating the files generated and how they are used.

dist_mem.ngc:
   Binary Xilinx implementation netlist file containing the information
   required to implement the module in a Xilinx (R) FPGA.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.