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https://opencores.org/ocsvn/diogenes/diogenes/trunk
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[/] [diogenes/] [trunk/] [vhdl/] [mysio.bgn] - Rev 236
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Release 9.2i - Bitgen J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s500e.nph' in environment
/opt/Xilinx92.
"mysio" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4
Opened constraints file mysio.pcf.
Mon Jan 28 21:06:21 2008
bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:1 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No mysio.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 1** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DCMShutdown | Disable** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| MultiBootMode | No* |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
Running DRC.
WARNING:PhysDesignRules:812 - Dangling pin <DOA14> on
block:<diogenes_cpu/pipestage3/cdmem/B10/diogenes_cpu/pipestage3/cdmem/B10.A>
:<RAMB16_RAMB16A>.
WARNING:PhysDesignRules:812 - Dangling pin <DOA15> on
block:<diogenes_cpu/pipestage3/cdmem/B10/diogenes_cpu/pipestage3/cdmem/B10.A>
:<RAMB16_RAMB16A>.
DRC detected 0 errors and 2 warnings.
Creating bit map...
Saving bit stream in "mysio.bit".
Bitstream generation is complete.