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https://opencores.org/ocsvn/diogenes/diogenes/trunk
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[/] [diogenes/] [trunk/] [vhdl/] [mysio.par] - Rev 212
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Release 9.2i par J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
thoreau:: Mon Jan 28 21:05:26 2008
par -w -intstyle ise -ol std -t 1 mysio_map.ncd mysio.ncd mysio.pcf
Constraints file: mysio.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/Xilinx92.
"mysio" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
Device speed data version: "PRODUCTION 1.26 2007-04-13".
Design Summary Report:
Number of External IOBs 35 out of 232 15%
Number of External Input IOBs 11
Number of External Input IBUFs 11
Number of LOCed External Input IBUFs 11 out of 11 100%
Number of External Output IOBs 24
Number of External Output IOBs 24
Number of LOCed External Output IOBs 24 out of 24 100%
Number of External Bidir IOBs 0
Number of BUFGMUXs 1 out of 24 4%
Number of RAMB16s 7 out of 20 35%
Number of Slices 784 out of 4656 16%
Number of SLICEMs 65 out of 2328 2%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
Starting initial Timing Analysis. REAL time: 3 secs
Finished initial Timing Analysis. REAL time: 3 secs
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:98b044) REAL time: 5 secs
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 5 secs
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 5 secs
Phase 4.2
.....
Phase 4.2 (Checksum:989e4f) REAL time: 6 secs
Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 6 secs
Phase 6.8
..................................................
..........
..................................................
...........
..................
...........................................................................................
Phase 6.8 (Checksum:c205ad) REAL time: 21 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 21 secs
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 30 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 30 secs
REAL time consumed by placer: 31 secs
CPU time consumed by placer: 31 secs
Writing design to file mysio.ncd
Total REAL time to Placer completion: 31 secs
Total CPU time to Placer completion: 31 secs
Starting Router
Phase 1: 6359 unrouted; REAL time: 34 secs
Phase 2: 5861 unrouted; REAL time: 35 secs
Phase 3: 1866 unrouted; REAL time: 36 secs
Phase 4: 1866 unrouted; (23259) REAL time: 37 secs
Phase 5: 1939 unrouted; (198) REAL time: 38 secs
Phase 6: 1948 unrouted; (0) REAL time: 38 secs
Phase 7: 0 unrouted; (0) REAL time: 41 secs
Phase 8: 0 unrouted; (0) REAL time: 42 secs
WARNING:Route:455 - CLK Net:diogenes_cpu/pipestage2/big_op<13> may have excessive skew because
0 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 43 secs
Total CPU time to Router completion: 43 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| gclk_BUFGP | BUFGMUX_X1Y11| No | 383 | 0.088 | 0.205 |
+---------------------+--------------+------+------+------------+-------------+
|diogenes_cpu/pipesta | | | | | |
| ge2/big_op<13> | Local| | 8 | 0.329 | 2.290 |
+---------------------+--------------+------+------+------------+-------------+
| was_button | Local| | 8 | 0.460 | 2.228 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
The Delay Summary Report
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 1.183
The MAXIMUM PIN DELAY IS: 4.331
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.777
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- ---------
2773 2441 981 64 3 0
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
NET "gclk_BUFGP/IBUFG" PERIOD = 12 ns HIG | SETUP | 0.040ns| 11.960ns| 0| 0
H 50% | HOLD | 0.814ns| | 0| 0
------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 44 secs
Total CPU time to PAR completion: 44 secs
Peak Memory Usage: 149 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 0
Writing design to file mysio.ncd
PAR done!
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