Subversion Repositories diogenes

version 3








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CLOCK_LIST_BEGIN
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
/mysio/gclk
/mysio/reset
/mysio/simulation
/mysio/rx
/mysio/tx
/mysio/test
/mysio/nreset
/mysio/wr_gen
/mysio/rd_gen
/mysio/rd_data
/mysio/wr_data
/mysio/addr
/mysio/mem_addr
/mysio/mem_dout
/mysio/mem_hi
/mysio/pmem_addr
/mysio/pmem_din
/mysio/pmem_dout
/mysio/pmem_we
/mysio/pmem_clk
/mysio/testout
/mysio/clk_cpu
/mysio/count
/mysio/extaddr
/mysio/extdin
/mysio/extdout
/mysio/extwr
/mysio/extrd
/mysio/mem_addr_cpu
/mysio/mem_dout_cpu
/mysio/reset_cpu
/mysio/cpu_running
/mysio/state
/mysio/mode
SIGNAL_ORDER_END
DIFFERENTIAL_CLKS_BEGIN
DIFFERENTIAL_CLKS_END
DIVIDERS_BEGIN
DIVIDERS_END
SIGPROPS_BEGIN
/mysio/gclk
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/mysio/reset
2
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/mysio/simulation
2
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/mysio/rx
2
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/mysio/tx
2
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/mysio/test
2
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/mysio/nreset
2
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/mysio/wr_gen
2
0
/mysio/rd_gen
2
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/mysio/rd_data
2
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/mysio/wr_data
2
0
/mysio/addr
2
0
/mysio/mem_addr
2
0
/mysio/mem_dout
2
0
/mysio/mem_hi
2
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/mysio/pmem_addr
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/mysio/pmem_din
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/mysio/pmem_dout
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/mysio/pmem_we
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/mysio/pmem_clk
2
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/mysio/testout
2
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/mysio/clk_cpu
2
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/mysio/count
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/mysio/extaddr
2
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/mysio/extdin
2
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/mysio/extdout
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/mysio/extwr
2
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/mysio/extrd
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/mysio/mem_addr_cpu
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/mysio/mem_dout_cpu
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/mysio/reset_cpu
2
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/mysio/cpu_running
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/mysio/state
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/mysio/mode
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SIGPROPS_END