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[/] [diogenes/] [trunk/] [vhdl/] [rs232.ise_ISE_Backup] - Rev 238

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PK

__REGISTRY__/PK
__REGISTRY__/idem/PK
_xmsgs/idem.xmsgs
s
PK
__REGISTRY__/hprep6/PK
_xmsgs/hprep6.xmsgs
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PK
__REGISTRY__/ngdbuild/PK
_xmsgs/ngdbuild.xmsgs
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PK
__REGISTRY__/xst/PK
_xmsgs/xst.xmsgs
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PK
 __REGISTRY__/_ProjRepoInternal_/PK
9.1i
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ISE_VERSION_LAST_SAVED_WITH
9.2i
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LastRepoDir
/home/andi/xilinx/diogenes/vhdl/
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OBJSTORE_VERSION
1.3
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REGISTRY_VERSION
1.1
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REPOSITORY_VERSION
1.1
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PK
__REGISTRY__/ProjectNavigator/PK
9.2i
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PK
__REGISTRY__/ngc2edif/PK
OUś00__REGISTRY__/ngc2edif/regkeysClientMessageOutputFile
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PK
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PK
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PK
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PK
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PK
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PK
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PK
__REGISTRY__/netgen/PK
_xmsgs/netgen.xmsgs
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PK
__REGISTRY__/runner/PK
_xmsgs/runner.xmsgs
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PK
__REGISTRY__/common/PK
false
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MessageCaptureEnabled
true
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MessageFilterFile
filter.filter
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MessageFilteringEnabled
false
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RunOnce
#/PnAutoRun/Scripts/RunOnce_tcl
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PK
 __REGISTRY__/HierarchicalDesign/PK
*__REGISTRY__/HierarchicalDesign/HDProject/PK

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CommandLine-Ngdbuild
ngdbuild -ise /home/andi/xilinx/rs232/rs232.ise -intstyle ise -dd _ngo -sd /home/andi/xilinx/rs232/cpu/ -nt timestamp -uc sio.ucf -p xc3s500e-fg320-4 mysio.ngc mysio.ngd
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CommandLine-Par

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CommandLine-Xst

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Previous-NGD
mysio_prev_built.ngd
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Previous-NGM

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Previous-Packed-NCD

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Previous-Routed-NCD

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PK
'__REGISTRY__/HierarchicalDesign/regkeysPK
__REGISTRY__/SrcCtrl/PK
__REGISTRY__/SrcCtrl/regkeysPK
__REGISTRY__/trce/PK
,,__REGISTRY__/trce/regkeysClientMessageOutputFile
_xmsgs/trce.xmsgs
s
PK
__REGISTRY__/XSLTProcess/PK
_xmsgs/XSLTProcess.xmsgs
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PK
!__REGISTRY__/ProjectNavigatorGui/PK
(__REGISTRY__/ProjectNavigatorGui/regkeysPK
__REGISTRY__/ngcbuild/PK
_xmsgs/ngcbuild.xmsgs
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PK
__REGISTRY__/WebTalk/PK
*__REGISTRY__/WebTalk/DesignDataCollection/PK
2012-11-27
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WebTalk-DataCollection-Project-ID
27258
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PK
__REGISTRY__/WebTalk/regkeysPK
__REGISTRY__/cpldfit/PK
_xmsgs/cpldfit.xmsgs
s
PK
__REGISTRY__/vlogcomp/PK
_xmsgs/vlogcomp.xmsgs
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PK
__REGISTRY__/dumpngdio/PK
_xmsgs/dumpngdio.xmsgs
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PK
__REGISTRY__/ISimPlugin/PK
__REGISTRY__/ISimPlugin/regkeysPK
__REGISTRY__/taengine/PK
_xmsgs/taengine.xmsgs
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PK

__OBJSTORE__/PK
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__OBJSTORE__/ProjectNavigator/PK
/__OBJSTORE__/ProjectNavigator/dpm_project_main/PK
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__OBJSTORE__/xreport/PK
artition Report" >   <view program="map" type="IOBProperties" inputState="Translated" file="mysio_map.mrp" label="IOB Properties" />   <view program="par" type="ConstraintsData" inputState="Mapped" file="mysio.par" label="Timing Constraints" />   <view program="par" type="PinoutData" inputState="Mapped" file="mysio.pad" label="Pinout Report" />   <view program="par" type="ClocksData" inputState="Mapped" file="mysio.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" />   <view program="ngdbuild" type="MessageList" inputState="Synthesized" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" />   <view program="map" type="MessageList" inputState="Translated" file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered" />   <view program="par" type="MessageList" inputState="Mapped" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" />   <view program="trce" type="MessageList" inputState="Routed" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" />   <view program="bitgen" type="MessageList" inputState="Routed" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" />   <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" type="MessageList" inputState="Current" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" />  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="mysio.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation" target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis" target="   HDL Analysis   " />    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />    <toc-item title="Partition Report" target="   Partition Report     " />    <toc-item title="Final Report" target="   Final Report   " />   <view program="ngdbuild" type="Report" inputState="Synthesized" file="mysio.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status" target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" type="Report" inputState="Translated" file="mysio_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors" target="Section 1 - " />    <toc-item title="Section 2: Warnings" target="Section 2 - " />    <toc-item title="Section 3: Infos" target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />    <toc-item title="Section 7: RPMs" target="Section 7 - " />    <toc-item title="Section 8: Guide Report" target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />    <toc-item title="Section 11: Timing Report" target="Section 11 - " />    <toc-item title="Section 12: Configuration String Information" target="Section 12 - " />   <view program="par" type="Report" inputState="Mapped" file="mysio.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Clock Report" target="Generating Clock Report" />    <toc-item title="Timing Results" target="Timing Score:" />    <toc-item title="Final Summary" target="Peak Memory Usage:" />   <view program="trce" type="Report" inputState="Routed" file="mysio.twr" label="Static Timing Report" >    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view program="bitgen" type="Report" inputState="Routed" file="mysio.bgn" label="Bitgen Report" >    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view hidden="true" program="isim" type="Secondary_Report" inputState="PreSynthesized" file="isim.log" label="ISIM Simulator Log" />   <view hidden="true" program="map" type="Secondary_Report" inputState="Translated" file="mysio_map.map" label="Map Log File" >    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary" target="Design Summary" />   <view hidden="true" program="xplorer" type="Secondary_Report" inputState="Routed" file="mysio_xplorer.rpt" label="Xplorer Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Translated" file="netgen/translate/mysio_translate.nlf" label="Post-Translate Simulation Model Report" />   <view hidden="true" program="trce" type="Secondary_Report" inputState="Mapped" file="mysio_preroute.twr" label="Post-Map Static Timing Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Mapped" file="netgen/map/mysio_map.nlf" label="Post-Map Simulation Model Report" />   <view hidden="true" program="par" type="Pad_Report" inputState="Mapped" file="mysio_pad.txt" label="Pad Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="mysio.unroutes" label="Unroutes Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="mysio.grf" label="Guide Results Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="mysio.dly" label="Asynchronous Delay Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="mysio.clk_rgn" label="Clock Region Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="netgen/par/mysio_timesim.nlf" label="Post-Route Simulation Model Report" />   <view hidden="true" program="xpwr" type="Report" inputState="Routed" file="mysio.pwr" label="Power Report" /> </body></report-views>PK
  <view program="map" inputState="Translated" type="IOBProperties" file="!module_name!_map.mrp" label="IOB Properties" />   <view program="par" inputState="Mapped" type="ConstraintsData" file="!module_name!.par" label="Timing Constraints" />   <view program="par" inputState="Mapped" type="PinoutData" file="!module_name!.pad" label="Pinout Report" />   <view program="par" inputState="Mapped" type="ClocksData" file="!module_name!.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered"/>   <view program="ngdbuild" inputState="Synthesized" type="MessageList" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered"/>   <view program="map" inputState="Translated" type="MessageList"  file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered"/>   <view program="par" inputState="Mapped" type="MessageList"  file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered"/>   <view program="trce" inputState="Routed" type="MessageList"  file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered"/>   <view program="bitgen" inputState="Routed" type="MessageList" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered"/>   <view program="implementation" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" inputState="Current" type="MessageList"  file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered"/>  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="!module_name!.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation"           target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis"              target="   HDL Analysis   " />    <toc-item title="HDL Synthesis"             target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis"    target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis"       target="   Low Level Synthesis   " />    <toc-item title="Partition Report"          target="   Partition Report     " />    <toc-item title="Final Report"              target="   Final Report   " />   <view program="ngdbuild" inputState="Synthesized" type="Report" file="!module_name!.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status"          target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" inputState="Translated" type="Report" file="!module_name!_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors"                             target="Section 1 - " />    <toc-item title="Section 2: Warnings"                           target="Section 2 - " />    <toc-item title="Section 3: Infos"                              target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary"              target="Section 4 - " />    <toc-item title="Section 5: Removed Logic"                      target="Section 5 - " />    <toc-item title="Section 6: IOB Properties"                     target="Section 6 - " />    <toc-item title="Section 7: RPMs"                               target="Section 7 - " />    <toc-item title="Section 8: Guide Report"                       target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary"   target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary"            target="Section 10 - " />    <toc-item title="Section 11: Timing Report"                     target="Section 11 - " />    <toc-item title="Section 12: Configuration String Information"  target="Section 12 - " />   <view program="par" inputState="Mapped" type="Report" file="!module_name!.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Partition Status"   target="Partition Implementation Status" />    <toc-item title="Clock Report"       target="Generating Clock Report" />    <toc-item title="Timing Results"     target="Timing Score:" />    <toc-item title="Final Summary"      target="Peak Memory Usage:" />   <view program="trce" inputState="Routed" type="Report" file="!module_name!.twr" label="Static Timing Report">    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view program="bitgen" inputState="Routed" type="Report" file="!module_name!.bgn" label="Bitgen Report">    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view program="isim" inputState="PreSynthesized" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" hidden="true"/>   <view program="map" inputState="Translated" type="Secondary_Report" file="!module_name!_map.map" label="Map Log File" hidden="true">    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary"     target="Design Summary" />   <view program="xplorer" inputState="Routed" type="Secondary_Report" file="!module_name!_xplorer.rpt" label="Xplorer Report" hidden="true"/>   <view program="netgen" inputState="Translated" type="Secondary_Report" file="netgen/translate/!module_name!_translate.nlf" label="Post-Translate Simulation Model Report" hidden="true"/>   <view program="trce" inputState="Mapped" type="Secondary_Report" file="!module_name!_preroute.twr" label="Post-Map Static Timing Report"  hidden="true"/>   <view program="netgen" inputState="Mapped" type="Secondary_Report" file="netgen/map/!module_name!_map.nlf" label="Post-Map Simulation Model Report" hidden="true"/>   <view program="par" inputState="Mapped" type="Pad_Report" file="!module_name!_pad.txt" label="Pad Report"  hidden="true"/>   <view program="par" inputState="Mapped" type="Secondary_Report" file="!module_name!.unroutes" label="Unroutes Report" hidden="true"/>   <view program="par" inputState="Mapped" type="Secondary_Report" file="!module_name!.grf" label="Guide Results Report" hidden="true"/>   <view program="par" inputState="Routed" type="Secondary_Report" file="!module_name!.dly" label="Asynchronous Delay Report" hidden="true"/>   <view program="par" inputState="Routed" type="Secondary_Report" file="!module_name!.clk_rgn" label="Clock Region Report" hidden="true"/>   <view program="netgen" inputState="Routed" type="Secondary_Report" file="netgen/par/!module_name!_timesim.nlf" label="Post-Route Simulation Model Report" hidden="true"/>   <view program="xpwr" inputState="Routed" type="Report" file="!module_name!.pwr" label="Power Report"  hidden="true"/> </body></report-views>PK

 !"#$%&'()*+,-./0123456789:;<=>?-@ABC+DEF+GHIJK+LMNOPQRSTUVWXYZPK

 !"#$%&'()*+,-./0123456789:;<=>?-@ABC+DEF+GHIJK+LMNOPQRSTUVWXYZPK
label="Partition Report" >   <view program="map" type="IOBProperties" inputState="Translated" file="sc_uart_map.mrp" label="IOB Properties" />   <view program="par" type="ConstraintsData" inputState="Mapped" file="sc_uart.par" label="Timing Constraints" />   <view program="par" type="PinoutData" inputState="Mapped" file="sc_uart.pad" label="Pinout Report" />   <view program="par" type="ClocksData" inputState="Mapped" file="sc_uart.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" />   <view program="ngdbuild" type="MessageList" inputState="Synthesized" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" />   <view program="map" type="MessageList" inputState="Translated" file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered" />   <view program="par" type="MessageList" inputState="Mapped" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" />   <view program="trce" type="MessageList" inputState="Routed" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" />   <view program="bitgen" type="MessageList" inputState="Routed" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" />   <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" type="MessageList" inputState="Current" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" />  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="sc_uart.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation" target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis" target="   HDL Analysis   " />    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />    <toc-item title="Partition Report" target="   Partition Report     " />    <toc-item title="Final Report" target="   Final Report   " />   <view program="ngdbuild" type="Report" inputState="Synthesized" file="sc_uart.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status" target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" type="Report" inputState="Translated" file="sc_uart_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors" target="Section 1 - " />    <toc-item title="Section 2: Warnings" target="Section 2 - " />    <toc-item title="Section 3: Infos" target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />    <toc-item title="Section 7: RPMs" target="Section 7 - " />    <toc-item title="Section 8: Guide Report" target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />    <toc-item title="Section 11: Timing Report" target="Section 11 - " />    <toc-item title="Section 12: Configuration String Information" target="Section 12 - " />   <view program="par" type="Report" inputState="Mapped" file="sc_uart.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Clock Report" target="Generating Clock Report" />    <toc-item title="Timing Results" target="Timing Score:" />    <toc-item title="Final Summary" target="Peak Memory Usage:" />   <view program="trce" type="Report" inputState="Routed" file="sc_uart.twr" label="Static Timing Report" >    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view program="bitgen" type="Report" inputState="Routed" file="sc_uart.bgn" label="Bitgen Report" >    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view hidden="true" program="isim" type="Secondary_Report" inputState="PreSynthesized" file="isim.log" label="ISIM Simulator Log" />   <view hidden="true" program="map" type="Secondary_Report" inputState="Translated" file="sc_uart_map.map" label="Map Log File" >    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary" target="Design Summary" />   <view hidden="true" program="xplorer" type="Secondary_Report" inputState="Routed" file="sc_uart_xplorer.rpt" label="Xplorer Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Translated" file="netgen/translate/sc_uart_translate.nlf" label="Post-Translate Simulation Model Report" />   <view hidden="true" program="trce" type="Secondary_Report" inputState="Mapped" file="sc_uart_preroute.twr" label="Post-Map Static Timing Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Mapped" file="netgen/map/sc_uart_map.nlf" label="Post-Map Simulation Model Report" />   <view hidden="true" program="par" type="Pad_Report" inputState="Mapped" file="sc_uart_pad.txt" label="Pad Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="sc_uart.unroutes" label="Unroutes Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="sc_uart.grf" label="Guide Results Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="sc_uart.dly" label="Asynchronous Delay Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="sc_uart.clk_rgn" label="Clock Region Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="netgen/par/sc_uart_timesim.nlf" label="Post-Route Simulation Model Report" />   <view hidden="true" program="xpwr" type="Report" inputState="Routed" file="sc_uart.pwr" label="Power Report" /> </body></report-views>PK

 !"#$%&'()*+,-./0123456789:;<=>?@ABC*DEF*GHIJK*LMNOPQRSTUVWXYZPK

 !"#$%&'()*+,-./0123456789:;<=>?-@ABC+DEF+GHIJK+LMNOPQRSTUVWXYZPK
 Report" >   <view program="map" type="IOBProperties" inputState="Translated" file="sio_map.mrp" label="IOB Properties" />   <view program="par" type="ConstraintsData" inputState="Mapped" file="sio.par" label="Timing Constraints" />   <view program="par" type="PinoutData" inputState="Mapped" file="sio.pad" label="Pinout Report" />   <view program="par" type="ClocksData" inputState="Mapped" file="sio.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" />   <view program="ngdbuild" type="MessageList" inputState="Synthesized" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" />   <view program="map" type="MessageList" inputState="Translated" file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered" />   <view program="par" type="MessageList" inputState="Mapped" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" />   <view program="trce" type="MessageList" inputState="Routed" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" />   <view program="bitgen" type="MessageList" inputState="Routed" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" />   <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" type="MessageList" inputState="Current" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" />  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="sio.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation" target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis" target="   HDL Analysis   " />    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />    <toc-item title="Partition Report" target="   Partition Report     " />    <toc-item title="Final Report" target="   Final Report   " />   <view program="ngdbuild" type="Report" inputState="Synthesized" file="sio.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status" target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" type="Report" inputState="Translated" file="sio_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors" target="Section 1 - " />    <toc-item title="Section 2: Warnings" target="Section 2 - " />    <toc-item title="Section 3: Infos" target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />    <toc-item title="Section 7: RPMs" target="Section 7 - " />    <toc-item title="Section 8: Guide Report" target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />    <toc-item title="Section 11: Timing Report" target="Section 11 - " />    <toc-item title="Section 12: Configuration String Information" target="Section 12 - " />   <view program="par" type="Report" inputState="Mapped" file="sio.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Clock Report" target="Generating Clock Report" />    <toc-item title="Timing Results" target="Timing Score:" />    <toc-item title="Final Summary" target="Peak Memory Usage:" />   <view program="trce" type="Report" inputState="Routed" file="sio.twr" label="Static Timing Report" >    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view program="bitgen" type="Report" inputState="Routed" file="sio.bgn" label="Bitgen Report" >    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view hidden="true" program="isim" type="Secondary_Report" inputState="PreSynthesized" file="isim.log" label="ISIM Simulator Log" />   <view hidden="true" program="map" type="Secondary_Report" inputState="Translated" file="sio_map.map" label="Map Log File" >    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary" target="Design Summary" />   <view hidden="true" program="xplorer" type="Secondary_Report" inputState="Routed" file="sio_xplorer.rpt" label="Xplorer Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Translated" file="netgen/translate/sio_translate.nlf" label="Post-Translate Simulation Model Report" />   <view hidden="true" program="trce" type="Secondary_Report" inputState="Mapped" file="sio_preroute.twr" label="Post-Map Static Timing Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Mapped" file="netgen/map/sio_map.nlf" label="Post-Map Simulation Model Report" />   <view hidden="true" program="par" type="Pad_Report" inputState="Mapped" file="sio_pad.txt" label="Pad Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="sio.unroutes" label="Unroutes Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="sio.grf" label="Guide Results Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="sio.dly" label="Asynchronous Delay Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="sio.clk_rgn" label="Clock Region Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="netgen/par/sio_timesim.nlf" label="Post-Route Simulation Model Report" />   <view hidden="true" program="xpwr" type="Report" inputState="Routed" file="sio.pwr" label="Power Report" /> </body></report-views>PK
__OBJSTORE__/common/PK
'__OBJSTORE__/common/HierarchicalDesign/PK
 __OBJSTORE__/HierarchicalDesign/PK
__OBJSTORE__/SrcCtrl/PK
"__OBJSTORE__/SrcCtrl/SavedOptions/PK
!__OBJSTORE__/ProjectNavigatorGui/PK











PK
TimingImplement Design/Place & Route/Generate Power DataImplement Design/Place & Route/MPPR Results UtilitiesImplement Design/TranslateSynthesize - XSTSynthesize - XST/Generate Post-Synthesis Simulation ModelUser ConstraintsDESUT_XCOCoregenXilinx ISE SimulatorPK
__OBJSTORE__/WebTalk/PK
__OBJSTORE__/PnAutoRun/PK
__OBJSTORE__/PnAutoRun/Scripts/PK
namespace eval Dpm {
proc GetIseVersion {} {
   set fsetName "fileset.txt"
   set fsetPath ""
   # Find the file in the Xilinx environment.
   # First, construct the environment path.
   set sep ":"; # Default to UNIX style seperator.
   if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
      set sep ";"; # Platform is a Windows variant, so use semi-colon.
   }
   set xilinxPath $::env(XILINX)
   if [info exists ::env(MYXILINX)] then {
      set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
   }
   # Now look in each path of the path until we find a match.
   foreach xilElem [split $xilinxPath $sep] {
      set checkPath ${xilElem}/$fsetName
      set checkPath [ string map { \\ / } $checkPath ]
      if { [file exists $checkPath] } {
         set fsetPath $checkPath
         break
      }
   }
   if { [string equal $fsetPath ""] } {
      puts "ERROR: Can not determine the ISE software version."
      return ""
   }
   if { [catch { open $fsetPath r } fset] } {
      puts "ERROR: Could not open $fsetPath: $fset"
      return ""
   }
   # have the file open, scan for the version entry.
   set sVersion ""
   while { ![eof $fset] } {
      set line [gets $fset]
      regexp {version=(.*)} $line match sVersion
         # The above doesn't stop looking in the file. This assumes that if
         # there are multiple version entries, the last one is the one we want.
   }
   close $fset
   return $sVersion
}
proc CheckForIron {project_name} {
   
   # Determine if the currently running version of ProjNav is earlier than Jade.
   set version [GetIseVersion]
   set dotLocation [string first "." $version]
   set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
   if {$versionBase < 9} {
      
      # The project file is newer than Iron, so take action to prevent the
      # file from being corrupted.
      # Make the file read-only.
      if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
         # The above will return 0 for a match to "windows" or "windows64".
         # This is the non-zero part of the if, for lin and sol.
         # Change the permissions to turn off writability.
         file attributes $project_name -permissions a-w
      } else {
         # On Windows, set file to read-only.
         file attributes $project_name -readonly 1
      }      
      
      # And tell the user about it.
      set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
      # In the console window
      puts $messageText
      # And with a GUI message box if possible.
      ::xilinx::Dpm::TOE::loadGuiLibraries
      set iInterface 0
      set messageDisplay 0
      if {[catch {
         set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
         set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
         if {$messageDisplay != 0} {
            # Managed to get a component to display a dialog, so use it
            set messageTitle "Incompatible Project Version (Newer)"
            set messageType 2
               # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
            set messageTimeout 300000
               # in milliseconds, 5 minutes
            set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
         }
      } catchResult]} {
         # There was an error, probably because we aren't in a GUI enviroment.
      } else {
         # All is well.
      }
      set messageDisplay 0
      set iInterface 0
   }
      
   return 1
}
}
}
::xilinx::Dpm::CheckForIronPK
__OBJSTORE__/ISimPlugin/PK
(__OBJSTORE__/ISimPlugin/SignalOrdering1/PK
nch/UUT/diogenes_cpu/pipestage3/result/sio_testbench/UUT/diogenes_cpu/pipestage3/regaddr/sio_testbench/UUT/diogenes_cpu/pipestage1/r/sio_testbench/UUT/diogenes_cpu/pipestage1/brzero/sio_testbench/UUT/diogenes_cpu/pipestage1/newpc/sio_testbench/UUT/diogenes_cpu/pipestage1/curpc/sio_testbench/UUT/testnch/UUT/diogenes_cpu/pipestage1/curpc/sio_testbench/UUT/test/sio_testbench/UUT/diogenes_cpu/extweio_testbench/UUT/diogenes_cpu/exten/sio_testbench/UUT/diogenes_cpu/extwees_cpu/pipestage3/cdmem/we/sio_testbench/UUT/diogenes_cpu/pipestage3/regaddr/sio_testbench/UUT/diogenes_cpu/pipestage2/regvalPK

PK

PK

 !"PK
1.1
REGISTRY_VERSION
1.1
OBJSTORE_VERSION
1.3
ISE_VERSION_CREATED_WITH
9.1i
ISE_VERSION_LAST_SAVED_WITH
9.2i
PKXR
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