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Release 9.2i Map J.36
Xilinx Mapping Report File for Design 'sio'
Design Information
------------------
Command Line : map -ise /home/andi/xilinx/rs232/rs232.ise -intstyle ise -p
xc3s500e-fg320-5 -cm area -pr b -k 4 -c 100 -o sio_map.ncd sio.ngd sio.pcf
Target Device : xc3s500e
Target Package : fg320
Target Speed : -5
Mapper Version : spartan3e -- $Revision: 1.1.1.1 $
Mapped Date : Tue Nov 13 12:05:41 2007
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 153 out of 9,312 1%
Number of 4 input LUTs: 171 out of 9,312 1%
Logic Distribution:
Number of occupied Slices: 140 out of 4,656 3%
Number of Slices containing only related logic: 140 out of 140 100%
Number of Slices containing unrelated logic: 0 out of 140 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 212 out of 9,312 2%
Number used as logic: 171
Number used as a route-thru: 40
Number used as Shift registers: 1
Number of bonded IOBs: 12 out of 232 5%
IOB Flip Flops: 9
Number of Block RAMs: 1 out of 20 5%
Number of GCLKs: 1 out of 24 4%
Total equivalent gate count for design: 68,222
Additional JTAG gate count for IOBs: 576
Peak Memory Usage: 145 MB
Total REAL time to MAP completion: 3 secs
Total CPU time to MAP completion: 3 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network mem_wr has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 3
more times for the following (max. 5 shown):
mem_data,
mem_en,
mem_addr
To see the details of these warning messages, please use the -detail switch.
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)
INFO:MapLib:159 - Net Timing constraints on signal clk are pushed forward
through input buffer.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.
Section 4 - Removed Logic Summary
---------------------------------
4 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND pmemc/GND
VCC pmemc/VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+-----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | IOB Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IBUF/IFD |
| | | | | Strength | Rate | | | Delay |
+-----------------------------------------------------------------------------------------------------------------------------------------+
| clk | IBUF | INPUT | LVTTL | | | | | 0 / 0 |
| reset | IBUF | INPUT | LVTTL | | | | PULLUP | 0 / 0 |
| rx | IBUF | INPUT | LVTTL | | | | | 0 / 0 |
| testout<0> | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
| testout<1> | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
| testout<2> | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
| testout<3> | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
| testout<4> | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
| testout<5> | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
| testout<6> | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
| testout<7> | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
| tx | IOB | OUTPUT | LVTTL | 4 | SLOW | OFF1 | | 0 / 0 |
+-----------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
This design was not run using timing mode.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.