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<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
        <Folder label="VERILOG Component Instantiation" treetype="folder">
                <Template label="pmem" treetype="template">
                </Template>
                <Template label="dist_mem" treetype="template">
                </Template>
                <Template label="video_ram" treetype="template">
                </Template>
        </Folder>
        <Folder label="VHDL Component Instantiation" treetype="folder">
                <Template label="pmem" treetype="template">
                </Template>
                <Template label="dist_mem" treetype="template">
                </Template>
                <Template label="video_ram" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component video_ram
    port (
    addra: IN std_logic_VECTOR(12 downto 0);
    addrb: IN std_logic_VECTOR(12 downto 0);
    clka: IN std_logic;
    clkb: IN std_logic;
    dinb: IN std_logic_VECTOR(7 downto 0);
    douta: OUT std_logic_VECTOR(7 downto 0);
    web: IN std_logic);
end component;

 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : video_ram
        port map (
            addra =&gt; addra,
            addrb =&gt; addrb,
            clka =&gt; clka,
            clkb =&gt; clkb,
            dinb =&gt; dinb,
            douta =&gt; douta,
            web =&gt; web);
 
                </Template>
        </Folder>
</RootFolder>