Subversion Repositories diogenes

# Date: Wed Jan 16 12:57:04 2008
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
SET workingdirectory = /home/andi/xilinx/rs232/vga/coregen/tmp