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The following files were generated for 'video_ram' in directory 
/home/andi/xilinx/rs232/vga/coregen/:

video_ram_readme.txt:
   Text file indicating the files generated and how they are used.

video_ram.mif:
   Memory Initialization File which is automatically generated by the
   CORE Generator System for some modules when a simulation flow is
   specified. A MIF data file is used to support HDL functional
   simulation of modules which use arrays of values.

video_ram.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

video_ram_xmdf.tcl:
   Please see the core data sheet.

video_ram.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

video_ram.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

video_ram.ngc:
   Binary Xilinx implementation netlist file containing the information
   required to implement the module in a Xilinx (R) FPGA.

video_ram_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.