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--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component video_ram
        port (
        addra: IN std_logic_VECTOR(12 downto 0);
        addrb: IN std_logic_VECTOR(12 downto 0);
        clka: IN std_logic;
        clkb: IN std_logic;
        dinb: IN std_logic_VECTOR(7 downto 0);
        douta: OUT std_logic_VECTOR(7 downto 0);
        web: IN std_logic);
end component;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : video_ram
                port map (
                        addra => addra,
                        addrb => addrb,
                        clka => clka,
                        clkb => clkb,
                        dinb => dinb,
                        douta => douta,
                        web => web);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file video_ram.vhd when simulating
-- the core, video_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".