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-- ***** BEGIN LICENSE BLOCK *****
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-- $Id: COUNT_UNIT.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * The Original Code is BBC Research and Development code.
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-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * Contributor(s): Peter Bleackley (Original author)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity COUNT_UNIT is
    Port ( INCREMENT : in std_logic;
           DECREMENT : in std_logic;
			  RESET :	in std_logic;
           CLOCK : in std_logic;
           OUTPUT : out std_logic;
           INCREMENT_CARRY : out std_logic;
           DECREMENT_CARRY : out std_logic);
end COUNT_UNIT;
 
architecture RTL of COUNT_UNIT is
	 component D_TYPE
	 port(D,CLOCK:	in std_logic;
	 Q:	out std_logic);
	 end component D_TYPE;
	 signal UPDATE:	std_logic :='0';
	 signal TOGGLE:	std_logic;
	 signal Q_VAL:	std_logic;
	 signal INVERSE:	std_logic;
	 signal NEWVAL : std_logic;
begin
 
-- combinatorial logic
 
	TOGGLE <= INCREMENT xor DECREMENT;
	INVERSE <= not Q_VAL;
	OUTPUT <= Q_VAL;
	INCREMENT_CARRY <= INCREMENT and not DECREMENT and Q_VAL;
	DECREMENT_CARRY <= DECREMENT and not INCREMENT and INVERSE;
	NEWVAL <= Q_VAL xor TOGGLE;
	UPDATE <= NEWVAL and not RESET;
 
 
 
 
 
-- The D_TYPE
 
FLIP_FLOP: D_TYPE
	port map(D => UPDATE,
	CLOCK => CLOCK,
	Q => Q_VAL);
 
end RTL;