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-- ***** BEGIN LICENSE BLOCK *****
-- 
-- $Id: D_TYPE.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * The contents of this file are subject to the Mozilla Public License
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-- * with the License. You may obtain a copy of the License at
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
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-- * Contributor(s): Peter Bleackley (Original author)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity D_TYPE is
    Port (
           D : in std_logic;
           CLOCK : in std_logic;
           Q : out std_logic);
end D_TYPE;
 
architecture RTL of D_TYPE is
begin
FLIP_FLOP: process(CLOCK)
begin
	if CLOCK'event and CLOCK = '1' then
	Q <= D;
	end if;
end process FLIP_FLOP;
 
end RTL;
 
configuration STANDARD of D_TYPE is
for RTL end for;
end configuration STANDARD;