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-- ***** BEGIN LICENSE BLOCK *****
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-- $Id: STORE_BLOCK.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * The Original Code is BBC Research and Development code.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * Contributor(s): Peter Bleackley (Original author)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity STORE_BLOCK is
    Port ( LOAD_IN : in std_logic;
           SHIFT_IN : in std_logic;
           SHIFT : in std_logic;
           ENABLE : in std_logic;
           CLK : in std_logic;
           OUTPUT : out std_logic);
end STORE_BLOCK;
 
architecture RTL of STORE_BLOCK is
	 component	ENABLEABLE_D_TYPE
	 port (DATA_IN, ENABLE, CLK: in std_logic;
			 DATA_OUT:	out std_logic);
	end component;
 
	signal LOAD_VALUE : std_logic;
begin
 
 
	STORAGE: ENABLEABLE_D_TYPE
	port map(DATA_IN => LOAD_VALUE,
				ENABLE => ENABLE,
				CLK => CLK,
				DATA_OUT => OUTPUT);
 
	SELECT_VALUE: process(SHIFT,SHIFT_IN,LOAD_IN)
	begin
	if SHIFT = '1' then
		LOAD_VALUE <= SHIFT_IN;
	else
		LOAD_VALUE <= LOAD_IN;
	end if;
	end process SELECT_VALUE;
 
 
 
 
end RTL;