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Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: context_manager.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "context_manager.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "context_manager"
Output Format                      : NGC
Target Device                      : xc2v2000-6-bg575

---- Source Options
Top Module Name                    : context_manager
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : context_manager.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work.
Architecture rtl of Entity divider is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work.
Architecture rtl of Entity updater is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work.
Architecture rtl of Entity halving_manager is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work.
Architecture rtl of Entity context_manager is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <context_manager> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 118: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 141: Index value(s) does not match array range, simulation mismatch.
Entity <context_manager> analyzed. Unit <context_manager> generated.

Analyzing Entity <DIVIDER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch.
Entity <DIVIDER> analyzed. Unit <DIVIDER> generated.

Analyzing Entity <UPDATER> (Architecture <rtl>).
Entity <UPDATER> analyzed. Unit <UPDATER> generated.

Analyzing Entity <HALVING_MANAGER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:1610 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
Entity <HALVING_MANAGER> analyzed. Unit <HALVING_MANAGER> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <HALVING_MANAGER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd".
    Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108.
    Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0051>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0052>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0053>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0054>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0055>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0056>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0057>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0058>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0059>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0060>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0061>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0062>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0063>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0064>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0065>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0066>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0067>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0068>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0069>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0070>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0071>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0072>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0073>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0074>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0075>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0076>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0077>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0078>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0079>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0080>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0081>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0082>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0084>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0085>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0087>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0088>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0089>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0090>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0091>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0092>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0093>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0094>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0095>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0096>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0097>.
    Found 3-bit addsub for signal <$n0098>.
    Found 3-bit addsub for signal <$n0100>.
    Found 3-bit addsub for signal <$n0101>.
    Found 3-bit addsub for signal <$n0102>.
    Found 3-bit addsub for signal <$n0103>.
    Found 3-bit addsub for signal <$n0104>.
    Found 3-bit addsub for signal <$n0105>.
    Found 3-bit addsub for signal <$n0106>.
    Found 3-bit addsub for signal <$n0107>.
    Found 3-bit addsub for signal <$n0108>.
    Found 3-bit addsub for signal <$n0109>.
    Found 3-bit addsub for signal <$n0110>.
    Found 3-bit addsub for signal <$n0111>.
    Found 3-bit addsub for signal <$n0112>.
    Found 3-bit addsub for signal <$n0113>.
    Found 3-bit addsub for signal <$n0114>.
    Found 3-bit addsub for signal <$n0115>.
    Found 3-bit addsub for signal <$n0116>.
    Found 3-bit addsub for signal <$n0117>.
    Found 3-bit addsub for signal <$n0118>.
    Found 3-bit addsub for signal <$n0119>.
    Found 3-bit addsub for signal <$n0120>.
    Found 3-bit addsub for signal <$n0121>.
    Found 3-bit addsub for signal <$n0122>.
    Found 3-bit addsub for signal <$n0123>.
    Found 3-bit addsub for signal <$n0124>.
    Found 3-bit addsub for signal <$n0125>.
    Found 3-bit addsub for signal <$n0126>.
    Found 3-bit addsub for signal <$n0127>.
    Found 3-bit addsub for signal <$n0128>.
    Found 3-bit addsub for signal <$n0129>.
    Found 3-bit addsub for signal <$n0130>.
    Found 3-bit addsub for signal <$n0131>.
    Found 3-bit addsub for signal <$n0132>.
    Found 3-bit addsub for signal <$n0133>.
    Found 3-bit addsub for signal <$n0134>.
    Found 3-bit addsub for signal <$n0135>.
    Found 3-bit addsub for signal <$n0136>.
    Found 3-bit addsub for signal <$n0137>.
    Found 3-bit addsub for signal <$n0138>.
    Found 3-bit addsub for signal <$n0139>.
    Found 3-bit addsub for signal <$n0140>.
    Found 3-bit addsub for signal <$n0141>.
    Found 3-bit addsub for signal <$n0142>.
    Found 3-bit addsub for signal <$n0143>.
    Found 3-bit addsub for signal <$n0144>.
    Found 8-bit comparator greater for signal <$n0147> created at line 99.
    Found 3-bit comparator greater for signal <$n0241> created at line 108.
    Found 1-bit register for signal <AFTER_TRIGGER>.
    Found 8-bit register for signal <DENOMINATOR>.
    Found 8-bit adder for signal <DENOMINATOR2>.
    Found 8-bit register for signal <NUMERATOR>.
    Found 8-bit adder for signal <NUMERATOR2>.
    Found 138-bit register for signal <SHIFTS>.
    Summary:
        inferred 139 D-type flip-flop(s).
        inferred  48 Adder/Subtractor(s).
        inferred   2 Comparator(s).
        inferred 141 Multiplexer(s).
Unit <HALVING_MANAGER> synthesized.


Synthesizing Unit <UPDATER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd".
    Found 1-bit register for signal <UPDATE>.
    Found 8-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
    Found 8-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
    Found 8-bit adder for signal <$n0009> created at line 50.
    Found 8-bit adder for signal <$n0011> created at line 72.
    Found 8-bit adder for signal <$n0012> created at line 83.
    Found 8-bit adder for signal <$n0013> created at line 61.
    Found 8-bit register for signal <DENOMINATOR2>.
    Found 8-bit register for signal <NUMERATOR1>.
    Found 8-bit register for signal <NUMERATOR2>.
    Found 8-bit register for signal <NUMERATOR3>.
    Found 8-bit register for signal <NUMERATOR4>.
    Found 1-bit xor2 for signal <UPDATE_SWITCH>.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   4 Adder/Subtractor(s).
        inferred  16 Multiplexer(s).
Unit <UPDATER> synthesized.


Synthesizing Unit <DIVIDER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <PRODUCT<23:16>> is assigned but never used.
WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used.
    Found 254x16-bit ROM for signal <$n0002> created at line 308.
    Found 16x8-bit multiplier for signal <$n0003> created at line 315.
    Found 8-bit subtractor for signal <INDEX>.
    Found 8-bit register for signal <NUMERATOR2>.
    Found 24-bit register for signal <PRODUCT>.
    Found 16-bit register for signal <RECIPROCAL>.
    Summary:
        inferred   1 ROM(s).
        inferred  40 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Multiplier(s).
Unit <DIVIDER> synthesized.


Synthesizing Unit <context_manager>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd".
    Found 46x16-bit dual-port block RAM for signal <PROBABILITY>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 46-word x 16-bit                    |          |
    | clock              | connected to signal <CLOCK>         | rise     |
    | dual clock         | connected to signal <CLOCK>         | rise     |
    | dual enable        | connected to signal <SET>           | high     |
    | write enable       | connected to signal <LOAD_DATA>     | high     |
    | address            | connected to signal <OLD_CONTEXT>   |          |
    | dual address       | connected to signal <CONTEXT_NUMBER> |          |
    | data in            | connected to signal <NEWPROB>       |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <RATIO>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Found 1-bit 46-to-1 multiplexer for signal <$n0003> created at line 141.
    Found 1-bit register for signal <CONTEXT_VALID>.
    Found 2-bit register for signal <DATA_READY>.
    Found 6-bit register for signal <OLD_CONTEXT>.
    Found 6-bit register for signal <READ_ADDRESS>.
    Found 46-bit register for signal <RESET_FLAGS>.
    Summary:
        inferred   1 RAM(s).
        inferred  61 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <context_manager> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
INFO:Xst:1647 - Data output of ROM <Mrom__n0002> in block <DIVIDER> is tied to register <RECIPROCAL> in block <DIVIDER>.
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
Advanced multiplier inference ...
    Found registered multiplier on signal <_n0003>:
        - 1 register level(s) found in a register connected to the multiplier macro ouput.
          Pushing register(s) into the multiplier macro.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Block RAMs                       : 2
 254x16-bit single-port block RAM  : 1
 46x16-bit dual-port block RAM     : 1
# Multipliers                      : 1
 16x8-bit registered multiplier    : 1
# Adders/Subtractors               : 53
 3-bit addsub                      : 46
 8-bit adder                       : 6
 8-bit subtractor                  : 1
# Registers                        : 107
 1-bit register                    : 51
 3-bit register                    : 46
 6-bit register                    : 2
 8-bit register                    : 8
# Comparators                      : 2
 3-bit comparator greater          : 1
 8-bit comparator greater          : 1
# Multiplexers                     : 50
 1-bit 46-to-1 multiplexer         : 1
 3-bit 4-to-1 multiplexer          : 46
 3-bit 46-to-1 multiplexer         : 1
 8-bit 4-to-1 multiplexer          : 2
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <context_manager> ...

Optimizing unit <HALVING_MANAGER> ...

Optimizing unit <UPDATER> ...

Optimizing unit <DIVIDER> ...
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register <PROBUPDATE_UPDATE> equivalent to <DATA_READY_0> has been removed
Register <DIVISION_NUMERATOR2_5> equivalent to <PROBUPDATE_NUMERATOR1_5> has been removed
Register <DIVISION_NUMERATOR2_7> equivalent to <PROBUPDATE_NUMERATOR1_7> has been removed
Register <DIVISION_NUMERATOR2_6> equivalent to <PROBUPDATE_NUMERATOR1_6> has been removed
Register <DIVISION_NUMERATOR2_0> equivalent to <PROBUPDATE_NUMERATOR1_0> has been removed
Register <DIVISION_NUMERATOR2_1> equivalent to <PROBUPDATE_NUMERATOR1_1> has been removed
Register <DIVISION_NUMERATOR2_2> equivalent to <PROBUPDATE_NUMERATOR1_2> has been removed
Register <DIVISION_NUMERATOR2_3> equivalent to <PROBUPDATE_NUMERATOR1_3> has been removed
Register <DIVISION_NUMERATOR2_4> equivalent to <PROBUPDATE_NUMERATOR1_4> has been removed
Found area constraint ratio of 100 (+ 5) on block context_manager, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : context_manager.ngr
Top Level Output File Name         : context_manager
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 21

Macro Statistics :
# RAM                              : 2
#      254x16-bit single-port block RAM: 1
#      46x16-bit dual-port block RAM: 1
# Registers                        : 163
#      1-bit register              : 115
#      3-bit register              : 46
#      6-bit register              : 2
# Multiplexers                     : 50
#      1-bit 46-to-1 multiplexer   : 1
#      3-bit 4-to-1 multiplexer    : 46
#      3-bit 46-to-1 multiplexer   : 1
#      8-bit 4-to-1 multiplexer    : 2
# Adders/Subtractors               : 7
#      8-bit adder                 : 6
#      8-bit subtractor            : 1
# Multipliers                      : 1
#      16x8-bit registered multiplier: 1
# Comparators                      : 2
#      3-bit comparator greater    : 1
#      8-bit comparator greater    : 1
# Xors                             : 92
#      1-bit xor3                  : 92

Cell Usage :
# BELS                             : 799
#      GND                         : 1
#      INV                         : 1
#      LUT1                        : 11
#      LUT1_L                      : 7
#      LUT2                        : 23
#      LUT3                        : 87
#      LUT3_D                      : 4
#      LUT3_L                      : 89
#      LUT4                        : 293
#      LUT4_D                      : 12
#      LUT4_L                      : 56
#      MUXCY                       : 42
#      MUXF5                       : 102
#      MUXF6                       : 19
#      MUXF7                       : 8
#      MUXF8                       : 4
#      VCC                         : 1
#      XORCY                       : 39
# FlipFlops/Latches                : 256
#      FD                          : 6
#      FDE                         : 6
#      FDR                         : 38
#      FDRE                        : 152
#      FDRSE                       : 1
#      FDS                         : 5
#      FDSE                        : 48
# RAMS                             : 2
#      RAMB16_S36                  : 1
#      RAMB16_S36_S36              : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 20
#      IBUF                        : 11
#      OBUF                        : 9
# MULTs                            : 1
#      MULT18X18S                  : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bg575-6 

 Number of Slices:                     316  out of  10752     2%  
 Number of Slice Flip Flops:           256  out of  21504     1%  
 Number of 4 input LUTs:               582  out of  21504     2%  
 Number of bonded IOBs:                 21  out of    408     5%  
 Number of BRAMs:                        2  out of     56     3%  
 Number of MULT18X18s:                   1  out of     56     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLOCK                              | BUFGP                  | 258   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 10.073ns (Maximum Frequency: 99.275MHz)
   Minimum input arrival time before clock: 10.619ns
   Maximum output required time after clock: 5.682ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
  Clock period: 10.073ns (frequency: 99.275MHz)
  Total number of paths / destination ports: 147629 / 423
-------------------------------------------------------------------------
Delay:               10.073ns (Levels of Logic = 17)
  Source:            REFRESH_SHIFTS_32_2 (FF)
  Destination:       PROBUPDATE_NUMERATOR4_7 (FF)
  Source Clock:      CLOCK rising
  Destination Clock: CLOCK rising

  Data Path: REFRESH_SHIFTS_32_2 to PROBUPDATE_NUMERATOR4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             4   0.449   0.717  REFRESH_SHIFTS_32_2 (REFRESH_SHIFTS_32_2)
     LUT3_L:I1->LO         1   0.347   0.000  REFRESH_CONTEXT<1>16 (REFRESH_MUX_BLOCK_N64)
     MUXF5:I0->O           1   0.345   0.000  REFRESH_CONTEXT<0>_rn_18 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57)
     MUXF6:I0->O           1   0.354   0.548  REFRESH_CONTEXT<2>_rn_7 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62)
     LUT4:I1->O            2   0.347   0.684  REFRESH__n024172 (CHOICE250)
     LUT4_L:I1->LO         1   0.347   0.000  REFRESH__n0241109_SW11_F (N764)
     MUXF5:I0->O           3   0.345   0.563  REFRESH__n0241109_SW11 (N673)
     LUT4_D:I2->O          9   0.347   0.665  REFRESH__n0145_1 (REFRESH__n01451)
     LUT4_L:I2->LO         1   0.347   0.000  REFRESH_NUMERATOR_OUT<2>12 (N590)
     MUXCY:S->O            1   0.235   0.000  PROBUPDATE_UPDATER__n0013<1>cy (PROBUPDATE_UPDATER__n0013<1>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBUPDATE_UPDATER__n0013<2>cy (PROBUPDATE_UPDATER__n0013<2>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBUPDATE_UPDATER__n0013<3>cy (PROBUPDATE_UPDATER__n0013<3>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBUPDATE_UPDATER__n0013<4>cy (PROBUPDATE_UPDATER__n0013<4>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBUPDATE_UPDATER__n0013<5>cy (PROBUPDATE_UPDATER__n0013<5>_cyo)
     XORCY:CI->O           2   0.824   0.744  PROBUPDATE_UPDATER__n0013<6>_xor (PROBUPDATE__n0013<6>)
     LUT1_L:I0->LO         1   0.347   0.000  PROBUPDATE__n0013<6>_rt (PROBUPDATE__n0013<6>_rt)
     MUXCY:S->O            0   0.235   0.000  PROBUPDATE_UPDATER__n0011<6>cy (PROBUPDATE_UPDATER__n0011<6>_cyo)
     XORCY:CI->O           1   0.824   0.000  PROBUPDATE_UPDATER__n0011<7>_xor (PROBUPDATE__n0011<7>)
     FDR:D                     0.293          PROBUPDATE_NUMERATOR4_7
    ----------------------------------------
    Total                     10.073ns (6.154ns logic, 3.919ns route)
                                       (61.1% logic, 38.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
  Total number of paths / destination ports: 94125 / 679
-------------------------------------------------------------------------
Offset:              10.619ns (Levels of Logic = 18)
  Source:            CONTEXT_NUMBER<1> (PAD)
  Destination:       PROBUPDATE_NUMERATOR4_7 (FF)
  Destination Clock: CLOCK rising

  Data Path: CONTEXT_NUMBER<1> to PROBUPDATE_NUMERATOR4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            48   0.653   1.060  CONTEXT_NUMBER_1_IBUF (CONTEXT_NUMBER_1_IBUF)
     LUT3_L:I0->LO         1   0.347   0.000  REFRESH_CONTEXT<1>15 (REFRESH_MUX_BLOCK_N63)
     MUXF5:I1->O           1   0.345   0.000  REFRESH_CONTEXT<0>_rn_18 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57)
     MUXF6:I0->O           1   0.354   0.548  REFRESH_CONTEXT<2>_rn_7 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62)
     LUT4:I1->O            2   0.347   0.684  REFRESH__n024172 (CHOICE250)
     LUT4_L:I1->LO         1   0.347   0.000  REFRESH__n0241109_SW11_F (N764)
     MUXF5:I0->O           3   0.345   0.563  REFRESH__n0241109_SW11 (N673)
     LUT4_D:I2->O          9   0.347   0.665  REFRESH__n0145_1 (REFRESH__n01451)
     LUT4_L:I2->LO         1   0.347   0.000  REFRESH_NUMERATOR_OUT<2>12 (N590)
     MUXCY:S->O            1   0.235   0.000  PROBUPDATE_UPDATER__n0013<1>cy (PROBUPDATE_UPDATER__n0013<1>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBUPDATE_UPDATER__n0013<2>cy (PROBUPDATE_UPDATER__n0013<2>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBUPDATE_UPDATER__n0013<3>cy (PROBUPDATE_UPDATER__n0013<3>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBUPDATE_UPDATER__n0013<4>cy (PROBUPDATE_UPDATER__n0013<4>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBUPDATE_UPDATER__n0013<5>cy (PROBUPDATE_UPDATER__n0013<5>_cyo)
     XORCY:CI->O           2   0.824   0.744  PROBUPDATE_UPDATER__n0013<6>_xor (PROBUPDATE__n0013<6>)
     LUT1_L:I0->LO         1   0.347   0.000  PROBUPDATE__n0013<6>_rt (PROBUPDATE__n0013<6>_rt)
     MUXCY:S->O            0   0.235   0.000  PROBUPDATE_UPDATER__n0011<6>cy (PROBUPDATE_UPDATER__n0011<6>_cyo)
     XORCY:CI->O           1   0.824   0.000  PROBUPDATE_UPDATER__n0011<7>_xor (PROBUPDATE__n0011<7>)
     FDR:D                     0.293          PROBUPDATE_NUMERATOR4_7
    ----------------------------------------
    Total                     10.619ns (6.358ns logic, 4.261ns route)
                                       (59.9% logic, 40.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
  Total number of paths / destination ports: 10 / 9
-------------------------------------------------------------------------
Offset:              5.682ns (Levels of Logic = 2)
  Source:            DATA_READY_0 (FF)
  Destination:       READY (PAD)
  Source Clock:      CLOCK rising

  Data Path: DATA_READY_0 to READY
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.449   0.760  DATA_READY_0 (DATA_READY_0)
     LUT2:I0->O            1   0.347   0.383  READY1 (READY_OBUF)
     OBUF:I->O                 3.743          READY_OBUF (READY)
    ----------------------------------------
    Total                      5.682ns (4.539ns logic, 1.143ns route)
                                       (79.9% logic, 20.1% route)

=========================================================================
CPU : 19.81 / 20.20 s | Elapsed : 20.00 / 20.00 s
 
--> 

Total memory usage is 126268 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   12 (   0 filtered)
Number of infos    :    3 (   0 filtered)