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Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: halving_manager.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "halving_manager.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "halving_manager"
Output Format                      : NGC
Target Device                      : xc2v2000-6-bg575

---- Source Options
Top Module Name                    : halving_manager
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : halving_manager.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work.
Architecture rtl of Entity halving_manager is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <halving_manager> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:1610 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
Entity <halving_manager> analyzed. Unit <halving_manager> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <halving_manager>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd".
    Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108.
    Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0051>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0052>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0053>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0054>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0055>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0056>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0057>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0058>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0059>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0060>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0061>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0062>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0063>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0064>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0065>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0066>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0067>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0068>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0069>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0070>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0071>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0072>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0073>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0074>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0075>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0076>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0077>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0078>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0079>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0080>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0081>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0082>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0084>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0085>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0087>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0088>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0089>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0090>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0091>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0092>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0093>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0094>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0095>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0096>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0097>.
    Found 3-bit addsub for signal <$n0098>.
    Found 3-bit addsub for signal <$n0100>.
    Found 3-bit addsub for signal <$n0101>.
    Found 3-bit addsub for signal <$n0102>.
    Found 3-bit addsub for signal <$n0103>.
    Found 3-bit addsub for signal <$n0104>.
    Found 3-bit addsub for signal <$n0105>.
    Found 3-bit addsub for signal <$n0106>.
    Found 3-bit addsub for signal <$n0107>.
    Found 3-bit addsub for signal <$n0108>.
    Found 3-bit addsub for signal <$n0109>.
    Found 3-bit addsub for signal <$n0110>.
    Found 3-bit addsub for signal <$n0111>.
    Found 3-bit addsub for signal <$n0112>.
    Found 3-bit addsub for signal <$n0113>.
    Found 3-bit addsub for signal <$n0114>.
    Found 3-bit addsub for signal <$n0115>.
    Found 3-bit addsub for signal <$n0116>.
    Found 3-bit addsub for signal <$n0117>.
    Found 3-bit addsub for signal <$n0118>.
    Found 3-bit addsub for signal <$n0119>.
    Found 3-bit addsub for signal <$n0120>.
    Found 3-bit addsub for signal <$n0121>.
    Found 3-bit addsub for signal <$n0122>.
    Found 3-bit addsub for signal <$n0123>.
    Found 3-bit addsub for signal <$n0124>.
    Found 3-bit addsub for signal <$n0125>.
    Found 3-bit addsub for signal <$n0126>.
    Found 3-bit addsub for signal <$n0127>.
    Found 3-bit addsub for signal <$n0128>.
    Found 3-bit addsub for signal <$n0129>.
    Found 3-bit addsub for signal <$n0130>.
    Found 3-bit addsub for signal <$n0131>.
    Found 3-bit addsub for signal <$n0132>.
    Found 3-bit addsub for signal <$n0133>.
    Found 3-bit addsub for signal <$n0134>.
    Found 3-bit addsub for signal <$n0135>.
    Found 3-bit addsub for signal <$n0136>.
    Found 3-bit addsub for signal <$n0137>.
    Found 3-bit addsub for signal <$n0138>.
    Found 3-bit addsub for signal <$n0139>.
    Found 3-bit addsub for signal <$n0140>.
    Found 3-bit addsub for signal <$n0141>.
    Found 3-bit addsub for signal <$n0142>.
    Found 3-bit addsub for signal <$n0143>.
    Found 3-bit addsub for signal <$n0144>.
    Found 8-bit comparator greater for signal <$n0147> created at line 99.
    Found 3-bit comparator greater for signal <$n0241> created at line 108.
    Found 1-bit register for signal <AFTER_TRIGGER>.
    Found 8-bit register for signal <DENOMINATOR>.
    Found 8-bit adder for signal <DENOMINATOR2>.
    Found 8-bit register for signal <NUMERATOR>.
    Found 8-bit adder for signal <NUMERATOR2>.
    Found 138-bit register for signal <SHIFTS>.
    Summary:
        inferred 139 D-type flip-flop(s).
        inferred  48 Adder/Subtractor(s).
        inferred   2 Comparator(s).
        inferred 141 Multiplexer(s).
Unit <halving_manager> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 48
 3-bit addsub                      : 46
 8-bit adder                       : 2
# Registers                        : 49
 1-bit register                    : 1
 3-bit register                    : 46
 8-bit register                    : 2
# Comparators                      : 2
 3-bit comparator greater          : 1
 8-bit comparator greater          : 1
# Multiplexers                     : 47
 3-bit 4-to-1 multiplexer          : 46
 3-bit 46-to-1 multiplexer         : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <halving_manager> ...
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block halving_manager, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : halving_manager.ngr
Top Level Output File Name         : halving_manager
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 43

Macro Statistics :
# Registers                        : 63
#      1-bit register              : 17
#      3-bit register              : 46
# Multiplexers                     : 47
#      3-bit 4-to-1 multiplexer    : 46
#      3-bit 46-to-1 multiplexer   : 1
# Adders/Subtractors               : 2
#      8-bit adder                 : 2
# Comparators                      : 2
#      3-bit comparator greater    : 1
#      8-bit comparator greater    : 1
# Xors                             : 92
#      1-bit xor3                  : 92

Cell Usage :
# BELS                             : 550
#      GND                         : 1
#      INV                         : 1
#      LUT1                        : 11
#      LUT2                        : 9
#      LUT3                        : 68
#      LUT3_D                      : 1
#      LUT3_L                      : 127
#      LUT4                        : 117
#      LUT4_D                      : 17
#      LUT4_L                      : 112
#      MUXCY                       : 14
#      MUXF5                       : 35
#      MUXF6                       : 15
#      MUXF7                       : 6
#      MUXF8                       : 3
#      VCC                         : 1
#      XORCY                       : 12
# FlipFlops/Latches                : 155
#      FDR                         : 1
#      FDRE                        : 152
#      FDSE                        : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 42
#      IBUF                        : 25
#      OBUF                        : 17
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bg575-6 

 Number of Slices:                     256  out of  10752     2%  
 Number of Slice Flip Flops:           155  out of  21504     0%  
 Number of 4 input LUTs:               462  out of  21504     2%  
 Number of bonded IOBs:                 43  out of    408    10%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLOCK                              | BUFGP                  | 155   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.759ns (Maximum Frequency: 147.951MHz)
   Minimum input arrival time before clock: 7.315ns
   Maximum output required time after clock: 11.248ns
   Maximum combinational path delay: 11.821ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
  Clock period: 6.759ns (frequency: 147.951MHz)
  Total number of paths / destination ports: 42357 / 308
-------------------------------------------------------------------------
Delay:               6.759ns (Levels of Logic = 8)
  Source:            SHIFTS_0_1 (FF)
  Destination:       SHIFTS_0_2 (FF)
  Source Clock:      CLOCK rising
  Destination Clock: CLOCK rising

  Data Path: SHIFTS_0_1 to SHIFTS_0_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             4   0.449   0.718  SHIFTS_0_1 (SHIFTS_0_1)
     LUT3_L:I1->LO         1   0.347   0.000  CONTEXT<4>31 (MUX_BLOCK_N38)
     MUXF5:I0->O           1   0.345   0.000  CONTEXT<1>_rn_14 (MUX_BLOCK_CONTEXT<1>_MUXF515)
     MUXF6:I0->O           1   0.354   0.000  CONTEXT<0>_rn_9 (MUX_BLOCK_CONTEXT<0>_MUXF67)
     MUXF7:I0->O           2   0.354   0.743  CONTEXT<2>_rn_3 (MUX_BLOCK_CONTEXT<2>_MUXF73)
     LUT4_L:I0->LO         1   0.347   0.000  _n0241106_1_F (N744)
     MUXF5:I0->O           4   0.345   0.579  _n0241106_1 (_n0241106)
     LUT4_D:I2->O         15   0.347   0.758  Ker601 (N60)
     LUT4:I2->O            3   0.347   0.535  _n0486 (_n0486)
     FDRE:CE                   0.190          SHIFTS_16_0
    ----------------------------------------
    Total                      6.759ns (3.425ns logic, 3.334ns route)
                                       (50.7% logic, 49.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
  Total number of paths / destination ports: 38734 / 464
-------------------------------------------------------------------------
Offset:              7.315ns (Levels of Logic = 9)
  Source:            CONTEXT<4> (PAD)
  Destination:       SHIFTS_0_2 (FF)
  Destination Clock: CLOCK rising

  Data Path: CONTEXT<4> to SHIFTS_0_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            53   0.653   1.069  CONTEXT_4_IBUF (CONTEXT_4_IBUF)
     LUT3_L:I0->LO         1   0.347   0.000  CONTEXT<4>25 (MUX_BLOCK_N32)
     MUXF5:I0->O           1   0.345   0.000  CONTEXT<1>_rn_11 (MUX_BLOCK_CONTEXT<1>_MUXF512)
     MUXF6:I1->O           1   0.354   0.000  CONTEXT<0>_rn_8 (MUX_BLOCK_CONTEXT<0>_MUXF66)
     MUXF7:I1->O           2   0.354   0.743  CONTEXT<2>_rn_3 (MUX_BLOCK_CONTEXT<2>_MUXF73)
     LUT4_L:I0->LO         1   0.347   0.000  _n0241106_1_F (N744)
     MUXF5:I0->O           4   0.345   0.579  _n0241106_1 (_n0241106)
     LUT4_D:I2->O         15   0.347   0.758  Ker601 (N60)
     LUT4:I2->O            3   0.347   0.535  _n0486 (_n0486)
     FDRE:CE                   0.190          SHIFTS_16_0
    ----------------------------------------
    Total                      7.315ns (3.629ns logic, 3.686ns route)
                                       (49.6% logic, 50.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
  Total number of paths / destination ports: 2514 / 17
-------------------------------------------------------------------------
Offset:              11.248ns (Levels of Logic = 10)
  Source:            SHIFTS_0_2 (FF)
  Destination:       DENOMINATOR_OUT<7> (PAD)
  Source Clock:      CLOCK rising

  Data Path: SHIFTS_0_2 to DENOMINATOR_OUT<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.449   0.701  SHIFTS_0_2 (SHIFTS_0_2)
     LUT3_L:I1->LO         1   0.347   0.000  CONTEXT<4>47 (MUX_BLOCK_N60)
     MUXF5:I0->O           1   0.345   0.000  CONTEXT<1>_rn_22 (MUX_BLOCK_CONTEXT<1>_MUXF523)
     MUXF6:I0->O           1   0.354   0.000  CONTEXT<0>_rn_16 (MUX_BLOCK_CONTEXT<0>_MUXF611)
     MUXF7:I0->O           2   0.354   0.000  CONTEXT<2>_rn_6 (MUX_BLOCK_CONTEXT<2>_MUXF75)
     MUXF8:I0->O           1   0.354   0.547  CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82)
     LUT4:I1->O           16   0.347   0.905  _n0241106 (CHOICE31)
     LUT4:I1->O            1   0.347   0.415  _n0145_SW1 (N702)
     LUT4:I3->O           16   0.347   0.964  _n0145 (_n0145)
     LUT3:I0->O            1   0.347   0.383  NUMERATOR_OUT<0>1 (NUMERATOR_OUT_0_OBUF)
     OBUF:I->O                 3.743          NUMERATOR_OUT_0_OBUF (NUMERATOR_OUT<0>)
    ----------------------------------------
    Total                     11.248ns (7.334ns logic, 3.914ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 2277 / 17
-------------------------------------------------------------------------
Delay:               11.821ns (Levels of Logic = 11)
  Source:            CONTEXT<4> (PAD)
  Destination:       DENOMINATOR_OUT<7> (PAD)

  Data Path: CONTEXT<4> to DENOMINATOR_OUT<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            53   0.653   1.069  CONTEXT_4_IBUF (CONTEXT_4_IBUF)
     LUT3_L:I0->LO         1   0.347   0.000  CONTEXT<4>41 (MUX_BLOCK_N54)
     MUXF5:I0->O           1   0.345   0.000  CONTEXT<1>_rn_19 (MUX_BLOCK_CONTEXT<1>_MUXF520)
     MUXF6:I1->O           1   0.354   0.000  CONTEXT<0>_rn_15 (MUX_BLOCK_CONTEXT<0>_MUXF610)
     MUXF7:I1->O           2   0.354   0.000  CONTEXT<2>_rn_6 (MUX_BLOCK_CONTEXT<2>_MUXF75)
     MUXF8:I0->O           1   0.354   0.547  CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82)
     LUT4:I1->O           16   0.347   0.905  _n0241106 (CHOICE31)
     LUT4:I1->O            1   0.347   0.415  _n0145_SW1 (N702)
     LUT4:I3->O           16   0.347   0.964  _n0145 (_n0145)
     LUT3:I0->O            1   0.347   0.383  NUMERATOR_OUT<0>1 (NUMERATOR_OUT_0_OBUF)
     OBUF:I->O                 3.743          NUMERATOR_OUT_0_OBUF (NUMERATOR_OUT<0>)
    ----------------------------------------
    Total                     11.821ns (7.538ns logic, 4.283ns route)
                                       (63.8% logic, 36.2% route)

=========================================================================
CPU : 15.17 / 15.55 s | Elapsed : 15.00 / 15.00 s
 
--> 

Total memory usage is 124220 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    1 (   0 filtered)