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-- ***** BEGIN LICENSE BLOCK *****
-- 
-- 
--  Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- 
--  The contents of this file are subject to the Mozilla Public License
--  Version 1.1 (the "License"); you may not use this file except in compliance
--  with the License. You may obtain a copy of the License at
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--  Software distributed under the License is distributed on an "AS IS" basis,
--  WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--  the specific language governing rights and limitations under the License.
-- 
--  The Original Code is BBC Research and Development code.
-- 
--  The Initial Developer of the Original Code is the British Broadcasting
--  Corporation.
--  Portions created by the Initial Developer are Copyright (C) 2006.
--  All Rights Reserved.
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--  Contributor(s): Peter Bleackley (Original author)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity EXP_GOLOMB_DECODER is
    Port ( ENABLE : in std_logic;
           DATA_IN : in std_logic;
           RESET : in std_logic;
           CLOCK : in std_logic;
           READY : out std_logic;
           DATA_OUT : out std_logic_vector(31 downto 0));
end EXP_GOLOMB_DECODER;
 
architecture RTL of EXP_GOLOMB_DECODER is
	signal DATA : std_logic_vector(31 downto 0);
	signal MODE : std_logic;
	signal CALC_COMPLETE : std_logic;
begin
 
READ_DATA : process (CLOCK)
begin
	if CLOCK'event and CLOCK = '1' then		--WHEN CLOCK EDGE DETECTED
		if RESET = '1' then		--SET ALL REGISTERS TO ZERO
			DATA <= ((0)=>'1', others => '0');
			DATA_OUT <= (others => '0');
			CALC_COMPLETE <= '0';
			MODE <= '0';
		elsif CALC_COMPLETE = '1' then
		  	DATA <= ((0)=> '1',others => '0');
			CALC_COMPLETE <= '0';
			MODE <= '0';
		elsif ENABLE = '1' then		--IF DATA IS BEING INPUT
			if MODE = '0' then		 --FOR "FOLLOW_ON" BITS
				CALC_COMPLETE <= DATA_IN;
				MODE <= '1';
				if DATA_IN = '1' then
					DATA_OUT <= DATA - "00000000000000000000000000000001";
				end if;
			else			  --IN MODE 1 (FOR DATA_BITS)
				DATA <= DATA (30 downto 0) & DATA_IN;
				MODE <= '0';
			end if;
		end if;
end if;
end process READ_DATA;
 
READY <= CALC_COMPLETE;
 
end RTL;