Subversion Repositories dma_ahb

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:31:23 2011
//--
//-- Source file: prgen_stall.v
//---------------------------------------------------------
 
 
 
module prgen_stall(clk,reset,din,stall,dout);
 
   parameter                  DEPTH   = 1;
 
   input               clk;
   input               reset;
 
   input               din;
   input               stall;
   output               dout;
 
 
 
   reg [DEPTH-1:0]           count;
   wire               pend;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       count <= #1 {DEPTH{1'b0}};
     else if (pend & (~stall))
       count <= #1 count - 1'b1;
     else if (din & stall)
       count <= #1 count + 1'b1;
 
   assign               pend = (|count);
   assign               dout = (din | pend) & (~stall);
 
 
 
 
 
endmodule