URL
https://opencores.org/ocsvn/dma_axi/dma_axi/trunk
Subversion Repositories dma_axi
[/] [dma_axi/] [trunk/] [src/] [dma_axi64/] [dma_axi64.v] - Rev 4
Compare with Previous | Blame | View Log
///////////////////////////////////////////////////////////////////// //// //// //// Author: Eyal Hochberg //// //// eyal@provartec.com //// //// //// //// Downloaded from: http://www.opencores.org //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Provartec LTD //// //// www.provartec.com //// //// info@provartec.com //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation.//// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more//// //// details. http://www.gnu.org/licenses/lgpl.html //// //// //// ///////////////////////////////////////////////////////////////////// //--------------------------------------------------------- //-- File generated by RobustVerilog parser //-- Version: 1.0 //-- Invoked Fri Mar 25 23:36:52 2011 //-- //-- Source file: dma.v //--------------------------------------------------------- module dma_axi64(clk,reset,scan_en,idle,INT,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,AWID0,AWADDR0,AWLEN0,AWSIZE0,AWVALID0,AWREADY0,WID0,WDATA0,WSTRB0,WLAST0,WVALID0,WREADY0,BID0,BRESP0,BVALID0,BREADY0,ARID0,ARADDR0,ARLEN0,ARSIZE0,ARVALID0,ARREADY0,RID0,RDATA0,RRESP0,RLAST0,RVALID0,RREADY0); `include "dma_axi64_defines.v" input clk; input reset; input scan_en; output idle; output [1-1:0] INT; input [31:1] periph_tx_req; output [31:1] periph_tx_clr; input [31:1] periph_rx_req; output [31:1] periph_rx_clr; input pclken; input psel; input penable; input [12:0] paddr; input pwrite; input [31:0] pwdata; output [31:0] prdata; output pslverr; output pready; output [`ID_BITS-1:0] AWID0; output [32-1:0] AWADDR0; output [`LEN_BITS-1:0] AWLEN0; output [`SIZE_BITS-1:0] AWSIZE0; output AWVALID0; input AWREADY0; output [`ID_BITS-1:0] WID0; output [64-1:0] WDATA0; output [64/8-1:0] WSTRB0; output WLAST0; output WVALID0; input WREADY0; input [`ID_BITS-1:0] BID0; input [1:0] BRESP0; input BVALID0; output BREADY0; output [`ID_BITS-1:0] ARID0; output [32-1:0] ARADDR0; output [`LEN_BITS-1:0] ARLEN0; output [`SIZE_BITS-1:0] ARSIZE0; output ARVALID0; input ARREADY0; input [`ID_BITS-1:0] RID0; input [64-1:0] RDATA0; input [1:0] RRESP0; input RLAST0; input RVALID0; output RREADY0; wire rd_port_num0; wire wr_port_num0; wire rd_port_num1; wire wr_port_num1; wire slv_rd_port_num0; wire slv_wr_port_num0; wire slv_rd_port_num1; wire slv_wr_port_num1; assign M0_AWID = 1'b0; assign M0_WID = 1'b0; assign M0_ARID = 1'b0; wire [`ID_BITS-1:0] M0_AWID; wire [32-1:0] M0_AWADDR; wire [`LEN_BITS-1:0] M0_AWLEN; wire [`SIZE_BITS-1:0] M0_AWSIZE; wire M0_AWVALID; wire M0_AWREADY; wire [`ID_BITS-1:0] M0_WID; wire [64-1:0] M0_WDATA; wire [64/8-1:0] M0_WSTRB; wire M0_WLAST; wire M0_WVALID; wire M0_WREADY; wire [`ID_BITS-1:0] M0_BID; wire [1:0] M0_BRESP; wire M0_BVALID; wire M0_BREADY; wire [`ID_BITS-1:0] M0_ARID; wire [32-1:0] M0_ARADDR; wire [`LEN_BITS-1:0] M0_ARLEN; wire [`SIZE_BITS-1:0] M0_ARSIZE; wire M0_ARVALID; wire M0_ARREADY; wire [`ID_BITS-1:0] M0_RID; wire [64-1:0] M0_RDATA; wire [1:0] M0_RRESP; wire M0_RLAST; wire M0_RVALID; wire M0_RREADY; wire [31:1] periph_tx_req; wire [31:1] periph_rx_req; wire [31:1] periph_tx_clr; wire [31:1] periph_rx_clr; assign AWID0 = M0_AWID; assign AWADDR0 = M0_AWADDR; assign AWLEN0 = M0_AWLEN; assign AWSIZE0 = M0_AWSIZE; assign AWVALID0 = M0_AWVALID; assign WID0 = M0_WID; assign WDATA0 = M0_WDATA; assign WSTRB0 = M0_WSTRB; assign WLAST0 = M0_WLAST; assign WVALID0 = M0_WVALID; assign BREADY0 = M0_BREADY; assign ARID0 = M0_ARID; assign ARADDR0 = M0_ARADDR; assign ARLEN0 = M0_ARLEN; assign ARSIZE0 = M0_ARSIZE; assign ARVALID0 = M0_ARVALID; assign RREADY0 = M0_RREADY; assign M0_AWREADY = AWREADY0; assign M0_WREADY = WREADY0; assign M0_BID = BID0; assign M0_BRESP = BRESP0; assign M0_BVALID = BVALID0; assign M0_ARREADY = ARREADY0; assign M0_RID = RID0; assign M0_RDATA = RDATA0; assign M0_RRESP = RRESP0; assign M0_RLAST = RLAST0; assign M0_RVALID = RVALID0; dma_axi64_dual_core dma_axi64_dual_core ( .clk(clk), .reset(reset), .scan_en(scan_en), .idle(idle), .INT(INT), .periph_tx_req(periph_tx_req), .periph_tx_clr(periph_tx_clr), .periph_rx_req(periph_rx_req), .periph_rx_clr(periph_rx_clr), .pclken(pclken), .psel(psel), .penable(penable), .paddr(paddr), .pwrite(pwrite), .pwdata(pwdata), .prdata(prdata), .pslverr(pslverr), .pready(pready), .rd_port_num0(rd_port_num0), .wr_port_num0(wr_port_num0), .rd_port_num1(rd_port_num1), .wr_port_num1(wr_port_num1), .M0_AWID(M0_AWID), .M0_AWADDR(M0_AWADDR), .M0_AWLEN(M0_AWLEN), .M0_AWSIZE(M0_AWSIZE), .M0_AWVALID(M0_AWVALID), .M0_AWREADY(M0_AWREADY), .M0_WID(M0_WID), .M0_WDATA(M0_WDATA), .M0_WSTRB(M0_WSTRB), .M0_WLAST(M0_WLAST), .M0_WVALID(M0_WVALID), .M0_WREADY(M0_WREADY), .M0_BID(M0_BID), .M0_BRESP(M0_BRESP), .M0_BVALID(M0_BVALID), .M0_BREADY(M0_BREADY), .M0_ARID(M0_ARID), .M0_ARADDR(M0_ARADDR), .M0_ARLEN(M0_ARLEN), .M0_ARSIZE(M0_ARSIZE), .M0_ARVALID(M0_ARVALID), .M0_ARREADY(M0_ARREADY), .M0_RID(M0_RID), .M0_RDATA(M0_RDATA), .M0_RRESP(M0_RRESP), .M0_RLAST(M0_RLAST), .M0_RVALID(M0_RVALID), .M0_RREADY(M0_RREADY) ); endmodule