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[/] [dmt_tx/] [trunk/] [myhdl/] [test/] [test_cmath.py] - Rev 30
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import unittest from myhdl import * from rtl.cmath import cadd, csub class TestCplxMath(unittest.TestCase): def test_cadd(self): def bench(): width = 4 m = 2**(width-1) a_re, a_im, b_re, b_im, y_re, y_im = [ Signal(intbv(0,min=-m, max=m)) for i in range(6)] overflow = Signal(bool(0)) cadd_inst = cadd(a_re,a_im,b_re,b_im,y_re,y_im, overflow, width) @instance def stimulus(): a_im.next = 1 b_re.next = 1 b_im.next = 1 overflow.next = False for ar in range(-m,m): for br in range(-m,m): a_re.next = ar b_re.next = br yield delay(10) yield delay(10) raise StopSimulation @instance def verify(): yield delay(5) while True: yre_exp = a_re + b_re yim_exp = a_im + b_im txt = "got: %s at: %d"%(overflow, now()) if yre_exp >= m: ovfl_re = True yre_exp = m-1 elif yre_exp < -m: ovfl_re = True yre_exp = -m else: ovfl_re = False self.assertEqual(y_re, yre_exp) if yim_exp >= m: ovfl_im = True yim_exp = m-1 elif yim_exp < -m: ovfl_im = True yim_exp = -m else: ovfl_im = False self.assertEqual(y_im, yim_exp) ovfl_exp = ovfl_re or ovfl_im self.assertEqual(ovfl_exp, overflow, txt) yield delay(10) return instances() tb = bench() #tb = traceSignals(bench) sim = Simulation(tb) sim.run() def test_csub(self): def bench(): width = 4 m = 2**(width-1) a_re, a_im, b_re, b_im, y_re, y_im = [ Signal(intbv(0,min=-m, max=m)) for i in range(6)] overflow = Signal(bool(0)) csub_inst = csub(a_re,a_im,b_re,b_im,y_re,y_im, overflow, width) @instance def stimulus(): a_im.next = 1 b_im.next = 1 overflow.next = False for ar in range(-m,m): for br in range(-m,m): a_re.next = ar b_re.next = br yield delay(10) yield delay(10) raise StopSimulation @instance def verify(): yield delay(5) while True: yre_exp = a_re - b_re yim_exp = a_im - b_im txt = "got: %s at: %d"%(overflow, now()) if yre_exp >= m: ovfl_re = True yre_exp = m-1 elif yre_exp < -m: ovfl_re = True yre_exp = -m else: ovfl_re = False self.assertEqual(y_re, yre_exp) if yim_exp >= m: ovfl_im = True yim_exp = m-1 elif yim_exp < -m: ovfl_im = True yim_exp = -m else: ovfl_im = False self.assertEqual(y_im, yim_exp) ovfl_exp = ovfl_re or ovfl_im self.assertEqual(ovfl_exp, overflow, txt) yield delay(10) return instances() tb = bench() #tb = traceSignals(bench) sim = Simulation(tb) sim.run() def test_cmult(self): pass
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