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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [fpga/] [memctrl-1/] [src/] [toplevel/] [memtest.ucf] - Rev 320
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#
# memtest.ucf -- user constraints for XSA-3S1000 + XST-3 board
#
#
# clock and reset
#
NET "clk_in" PERIOD = 10.0ns HIGH 40%;
NET "clk_in" LOC = "t9";
NET "rst_inout_n" LOC = "d15";
#
# SDRAM
#
NET "sdram_clk" LOC = "e10";
NET "sdram_fb" LOC = "n8";
NET "sdram_cke" LOC = "d7";
NET "sdram_cs_n" LOC = "b8";
NET "sdram_ras_n" LOC = "a9";
NET "sdram_cas_n" LOC = "a10";
NET "sdram_we_n" LOC = "b10";
NET "sdram_ba<1>" LOC = "c7";
NET "sdram_ba<0>" LOC = "a7";
NET "sdram_a<12>" LOC = "c6";
NET "sdram_a<11>" LOC = "c5";
NET "sdram_a<10>" LOC = "b6";
NET "sdram_a<9>" LOC = "a3";
NET "sdram_a<8>" LOC = "c2";
NET "sdram_a<7>" LOC = "d3";
NET "sdram_a<6>" LOC = "e4";
NET "sdram_a<5>" LOC = "c1";
NET "sdram_a<4>" LOC = "e3";
NET "sdram_a<3>" LOC = "e6";
NET "sdram_a<2>" LOC = "b4";
NET "sdram_a<1>" LOC = "a4";
NET "sdram_a<0>" LOC = "b5";
NET "sdram_udqm" LOC = "d9";
NET "sdram_ldqm" LOC = "c10";
NET "sdram_dq<15>" LOC = "f13";
NET "sdram_dq<14>" LOC = "f12";
NET "sdram_dq<13>" LOC = "c16";
NET "sdram_dq<12>" LOC = "d14";
NET "sdram_dq<11>" LOC = "b14";
NET "sdram_dq<10>" LOC = "c12";
NET "sdram_dq<9>" LOC = "b12";
NET "sdram_dq<8>" LOC = "b11";
NET "sdram_dq<7>" LOC = "d10";
NET "sdram_dq<6>" LOC = "c11";
NET "sdram_dq<5>" LOC = "a12";
NET "sdram_dq<4>" LOC = "d11";
NET "sdram_dq<3>" LOC = "b13";
NET "sdram_dq<2>" LOC = "a14";
NET "sdram_dq<1>" LOC = "d12";
NET "sdram_dq<0>" LOC = "c15";
#
# 7 segment LED
#
NET "ssl<6>" LOC = "r10";
NET "ssl<5>" LOC = "t7";
NET "ssl<4>" LOC = "p10";
NET "ssl<3>" LOC = "r7";
NET "ssl<2>" LOC = "n6";
NET "ssl<1>" LOC = "m11";
NET "ssl<0>" LOC = "m6";
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