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[/] [eco32/] [trunk/] [fpga/] [experiments/] [memctrl/] [sim/] [memctrl-0/] [memtest.cfg] - Rev 320

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[timestart] 0
[size] 1280 725
[pos] -1 -1
*-16.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] memtest.
[treeopen] memtest.ramctrl_1.
@28
memtest.clk
memtest.rst_in
memtest.rst
@200
--- INST RD --
@28
memtest.inst_stb
@22
memtest.inst_addr[25:0]
memtest.inst_to_cache[63:0]
@28
memtest.inst_ack
memtest.inst_timeout
@200
--- DATA RD/WR --
@28
memtest.data_stb
memtest.data_we
@22
memtest.data_addr[25:0]
memtest.data_to_mctrl[63:0]
memtest.data_to_cache[63:0]
@28
memtest.data_ack
memtest.data_timeout
@200
--- TEST RESULT --
@28
memtest.test_ended
memtest.test_error
@200
---- RAM CHIP --
@28
memtest.ramctrl_1.ram_stb
memtest.ramctrl_1.ram_we
@22
memtest.ramctrl_1.ram_addr[22:0]
memtest.ramctrl_1.ram_dout[31:0]
memtest.ramctrl_1.ram_din[31:0]
@28
memtest.ramctrl_1.ram_ack

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