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[/] [eco32/] [trunk/] [fpga/] [mc/] [boards/] [xsa-xst-3/] [doc/] [dac/] [README] - Rev 329

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Timing Parameters
-----------------

clk = 50 MHz (20 nsec)
mclk = clk / 4 = 12.5 MHz (80 nsec)
sclk = mclk / 4 = 3.125 MHz (320 nsec)
lrck = sclk / 64 = 48.828 kHz (20.48 usec)

==>

fs = 48.828 kHz
mclk = 256 * fs = 12.5 MHz
sclk = 64 * fs = 3.125 MHz

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