Subversion Repositories ecpu_alu

$date
        Wed Apr  1 16:53:10 2009
$end
$version
        Icarus Verilog
$end
$timescale
        1ps
$end
$scope module alu_tb $end
$var wire 1 ! C $end
$var wire 1 " V $end
$var wire 8 # Y [7:0] $end
$var wire 1 $ Z $end
$var reg 8 % A [7:0] $end
$var reg 8 & A_u [7:0] $end
$var reg 8 ' B [7:0] $end
$var reg 8 ( B_u [7:0] $end
$var reg 1 ) CLK $end
$var reg 1 * CLR $end
$var reg 4 + S [3:0] $end
$var reg 8 , Y_u [7:0] $end
$var reg 8 - aa [7:0] $end
$var reg 8 . bb [7:0] $end
$var reg 1 / check_here $end
$var reg 1 0 clrc $end
$var reg 32 1 count [31:0] $end
$var reg 32 2 errors_found [31:0] $end
$var reg 1 3 finished $end
$var reg 32 4 infile [31:0] $end
$var reg 1 5 last_CLR $end
$var reg 32 6 last_ss [31:0] $end
$var reg 8 7 op1 [7:0] $end
$var reg 8 8 op2 [7:0] $end
$var reg 32 9 outfile [31:0] $end
$var reg 32 : random_count [31:0] $end
$var reg 1 ; random_mode $end
$var reg 32 < random_number [31:0] $end
$var reg 8 = result [7:0] $end
$var reg 8 > result_u [7:0] $end
$var reg 32 ? ss [31:0] $end
$var reg 1 @ started $end
$var reg 32 A success [31:0] $end
$scope function bas $end
$var reg 8 B a1 [7:0] $end
$var reg 8 C bas [7:0] $end
$var reg 1 D direction $end
$var reg 8 E shift_size [7:0] $end
$var reg 8 F tmp [7:0] $end
$var reg 32 G tmp2 [31:0] $end
$upscope $end
$scope function get_random_opcode $end
$var reg 32 H get_random_opcode [32:1] $end
$var reg 32 I myseed [31:0] $end
$var reg 32 J tmp [31:0] $end
$upscope $end
$scope function string2opcode $end
$var reg 4 K opcode [3:0] $end
$var reg 32 L s [31:0] $end
$var reg 4 M string2opcode [3:0] $end
$upscope $end
$scope module this_record $end
$var reg 8 N A [7:0] $end
$var reg 8 O B [7:0] $end
$var reg 32 P S [31:0] $end
$var reg 8 Q Y [7:0] $end
$upscope $end
$scope module next_record $end
$var reg 8 R A [7:0] $end
$var reg 8 S B [7:0] $end
$var reg 32 T S [31:0] $end
$var reg 8 U Y [7:0] $end
$upscope $end
$scope module alu_inst0 $end
$var wire 8 V A [7:0] $end
$var wire 8 W B [7:0] $end
$var wire 1 ! C $end
$var wire 1 X CLK $end
$var wire 1 Y CLR $end
$var wire 4 Z S [3:0] $end
$var wire 1 " V $end
$var wire 8 [ Y [7:0] $end
$var wire 1 $ Z $end
$var wire 1 \ add_AB $end
$var wire 1 ] and_AB $end
$var wire 1 ^ clr_ALL $end
$var wire 1 _ clr_C $end
$var wire 1 ` clr_V $end
$var wire 1 a clr_Z $end
$var wire 1 b cmp_AB $end
$var wire 1 c cpl_A $end
$var wire 1 d cpl_B $end
$var wire 1 e dec_A $end
$var wire 1 f dec_B $end
$var wire 1 g inc_A $end
$var wire 1 h inc_B $end
$var wire 1 i load_inputs $end
$var wire 1 j load_outputs $end
$var wire 1 k mul_AB $end
$var wire 1 l or_AB $end
$var wire 1 m reset $end
$var wire 1 n sl_AB $end
$var wire 1 o sr_AB $end
$var wire 1 p sub_AB $end
$var wire 1 q xor_AB $end
$scope module controller $end
$var wire 1 \ add_AB $end
$var wire 1 ] and_AB $end
$var wire 1 X clk $end
$var wire 1 ^ clr $end
$var wire 1 _ clr_C $end
$var wire 1 ` clr_V $end
$var wire 1 a clr_Z $end
$var wire 1 b cmp_AB $end
$var wire 1 c cpl_A $end
$var wire 1 d cpl_B $end
$var wire 1 e dec_A $end
$var wire 1 f dec_B $end
$var wire 1 g inc_A $end
$var wire 1 h inc_B $end
$var wire 1 k mul_AB $end
$var wire 4 r opcode [3:0] $end
$var wire 1 l or_AB $end
$var wire 1 m reset $end
$var wire 1 n sl_AB $end
$var wire 1 o sr_AB $end
$var wire 1 p sub_AB $end
$var wire 1 q xor_AB $end
$var reg 1 s load_inputs $end
$var reg 1 t load_outputs $end
$var reg 4 u next_opcode [3:0] $end
$var reg 65538 v opcode_sel [65537:0] $end
$var reg 4 w this_opcode [3:0] $end
$upscope $end
$scope module datapath $end
$var wire 8 x A [7:0] $end
$var wire 8 y B [7:0] $end
$var wire 1 ! C $end
$var wire 1 " V $end
$var wire 8 z Y [7:0] $end
$var wire 1 $ Z $end
$var wire 1 \ add_AB $end
$var wire 1 { adderORsel $end
$var wire 1 | adderXORsel $end
$var wire 8 } adder_in_a [7:0] $end
$var wire 8 ~ adder_in_b [7:0] $end
$var wire 8 !" adder_out [7:0] $end
$var wire 8 "" alu_out [7:0] $end
$var wire 1 ] and_AB $end
$var wire 1 #" carry $end
$var wire 1 $" carry_in $end
$var wire 9 %" carry_out [8:0] $end
$var wire 1 X clk $end
$var wire 1 ^ clr $end
$var wire 1 _ clr_C $end
$var wire 1 ` clr_V $end
$var wire 1 a clr_Z $end
$var wire 1 b cmp_AB $end
$var wire 1 c cpl_A $end
$var wire 1 d cpl_B $end
$var wire 1 e dec_A $end
$var wire 1 f dec_B $end
$var wire 1 g inc_A $end
$var wire 1 h inc_B $end
$var wire 1 i load_inputs $end
$var wire 1 j load_outputs $end
$var wire 8 &" logic0 [7:0] $end
$var wire 8 '" logic1 [7:0] $end
$var wire 1 k mul_AB $end
$var wire 1 l or_AB $end
$var wire 1 m reset $end
$var wire 1 (" shifter_carry $end
$var wire 1 )" shifter_direction $end
$var wire 8 *" shifter_inA [7:0] $end
$var wire 8 +" shifter_inB [7:0] $end
$var wire 8 ," shifter_out [7:0] $end
$var wire 1 n sl_AB $end
$var wire 1 o sr_AB $end
$var wire 1 p sub_AB $end
$var wire 1 q xor_AB $end
$var reg 8 -" Areg [7:0] $end
$var reg 8 ." Breg [7:0] $end
$var reg 1 /" Creg $end
$var reg 1 0" Vreg $end
$var reg 8 1" Yreg [7:0] $end
$var reg 1 2" Zreg $end
$scope module adder $end
$var wire 1 { ORsel $end
$var wire 1 | XORsel $end
$var wire 8 3" XandY [7:0] $end
$var wire 8 4" XorY [7:0] $end
$var wire 8 5" XxorY [7:0] $end
$var wire 8 6" and_result [7:0] $end
$var wire 1 $" carry_in $end
$var wire 8 7" or_result [7:0] $end
$var wire 8 8" x [7:0] $end
$var wire 8 9" xor_result [7:0] $end
$var wire 8 :" y [7:0] $end
$var reg 9 ;" carry_out [8:0] $end
$var reg 32 <" i [31:0] $end
$var reg 8 =" z [7:0] $end
$upscope $end
$scope module shifter $end
$var wire 1 X clk $end
$var wire 1 )" direction $end
$var wire 8 >" x [7:0] $end
$var wire 8 ?" y [7:0] $end
$var reg 1 @" c $end
$var reg 8 A" y_tmp [7:0] $end
$var reg 8 B" z [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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