Subversion Repositories ecpu_alu

Veriwell version 2.8.7, 
Copyright (C) 1993-2008 Elliot Mednick and Mark Hummel

Veriwell comes with ABSOLUTELY NO WARRANTY; This is free
software, and you are welcome to redistribute it under the
terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License,
or (at your option) any later version. 

lxt  support compiled in
lxt2 support compiled in

Entering Phase I...
Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/..//barrel_shifter/simple/barrel_shifter_simple.v
Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/..//adder/alu_adder.v
Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu_datapath.v
Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu_controller.v
Compiling included source file '/home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu_controller.vh'
Continuing compilation of source file '/home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu_controller.v'
Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu.v

Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
   alu

0 Errors, 0 Warnings, Compile time = 0.0, Load time = 0.0, Simulation time = 0.0

Normal exit
Thank you for using Veriwell