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[/] [edge/] [trunk/] [HW/] [Boards/] [Atlys/] [EdgeMemMap.bmm] - Rev 2
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//////////////////////////////////////////////////////////////////
// //
// Memory map for Edge project //
// //
// This file is part of the Edge project //
// http://www.opencores.org/project,edge //
// //
// Description //
// Memory map for Edge project to map elf files to BRAMS on //
// Atlys board.
// //
// Author(s): //
// - Hesham AL-Matary, heshamelmatary@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2014 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
ADDRESS_SPACE text RAMB16 [0x00000000:0x000007FF]
BUS_BLOCK
ins_mem/ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram [31:0] PLACED = X0Y8;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
ADDRESS_SPACE rodata RAMB8 [0x00000800:0x00000BFF]
BUS_BLOCK
mem_io/rodata/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM9.ram [7:0] LOC = X1Y12;
END_BUS_BLOCK;
END_ADDRESS_SPACE;