URL
https://opencores.org/ocsvn/edge/edge/trunk
Subversion Repositories edge
[/] [edge/] [trunk/] [HW/] [Verilog/] [shift_left.v] - Rev 2
Compare with Previous | Blame | View Log
////////////////////////////////////////////////////////////////// // // // Shift by 2 bits // // // // This file is part of the Edge project // // http://www.opencores.org/project,edge // // // // Description // // Shifting input by 2 bits (Should be supressed in future) // // // // Author(s): // // - Hesham AL-Matary, heshamelmatary@gmail.com // // // ////////////////////////////////////////////////////////////////// // // // Copyright (C) 2014 Authors and OPENCORES.ORG // // // // This source file may be used and distributed without // // restriction provided that this copyright statement is not // // removed from the file and that any derivative work contains // // the original copyright notice and the associated disclaimer. // // // // This source file is free software; you can redistribute it // // and/or modify it under the terms of the GNU Lesser General // // Public License as published by the Free Software Foundation; // // either version 2.1 of the License, or (at your option) any // // later version. // // // // This source is distributed in the hope that it will be // // useful, but WITHOUT ANY WARRANTY; without even the implied // // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // // PURPOSE. See the GNU Lesser General Public License for more // // details. // // // // You should have received a copy of the GNU Lesser General // // Public License along with this source; if not, download it // // from http://www.opencores.org/lgpl.shtml // // // ////////////////////////////////////////////////////////////////// module shift_left2 # ( parameter N = 32 ) ( input[N-1:0] a, output[N-1:0] out ); assign out = {a[29:0],2'b00}; endmodule