Subversion Repositories embedded_risc

0000_0000_0000_0000_0000_0000_0000_0111   //000  00 000007 LDA  acc <- (7)      start testing the dma Registers
0000_0001_0000_1000_0000_0000_0000_0001   //001  01 080001 STO  (80001) <- acc
0000_0000_0000_0000_0000_0000_0000_1000   //002  00 000008 LDA  acc <- (8)
0000_0001_0000_1000_0000_0000_0000_0010   //003  01 080002 STO  (80002) <- acc
0000_0000_0000_0000_0000_0000_0000_1001   //004  00 000009 LDA  acc <- (9)
0000_0001_0000_1000_0000_0000_0000_0011   //005  01 080003 STO  (80003) <- acc
0000_0100_0000_0000_0000_0000_0000_1010   //006  04 00000a JMP  (00A)
0000_0000_0000_0000_0000_0000_0001_0000   //007 Value is 10
0000_0000_0000_0000_0000_0000_0001_0001   //008 Value is 11
0000_0000_0000_0000_0000_0000_0001_0010   //009 Value is 12
0000_0000_0000_1000_0000_0000_0000_0001   //00a  01 080001 LDA  acc <- (80001)
0000_0000_0000_1000_0000_0000_0000_0010   //00b  01 080002 LDA  acc <- (80002)
0000_0000_0000_1000_0000_0000_0000_0011   //00c  01 080003 LDA  acc <- (80003)  end testing the dma Registers
0000_0000_0000_0000_0000_0000_0001_0100   //00d  00 000014 LDA  acc <- (14)     start testing the Flash Registers
0000_0001_0000_1000_0000_0000_0000_1000   //00e  01 080008 STO  (80008) <- acc
0000_0000_0000_0000_0000_0000_0001_0101   //00f  00 000015 LDA  acc <- (15)
0000_0001_0000_1000_0000_0000_0000_1001   //010  01 080009 STO  (80009) <- acc
0000_0000_0000_0000_0000_0000_0001_0110   //011  00 000016 LDA  acc <- (16)
0000_0001_0000_1000_0000_0000_0000_1010   //012  01 08000a STO  (8000a) <- acc
0000_0100_0000_0000_0000_0000_0001_0111   //013  04 000017 JMP  (017)
0000_0000_0000_0000_0000_0000_0001_0011   //014 Value is 13
0000_0000_0000_0000_0000_0000_0001_0100   //015 Value is 14
0000_0000_0000_0000_0000_0000_0001_0101   //016 Value is 15
0000_0000_0000_1000_0000_0000_0000_1000   //017  01 080008 LDA  acc <- (80008)
0000_0000_0000_1000_0000_0000_0000_1001   //018  01 080009 LDA  acc <- (80009)
0000_0000_0000_1000_0000_0000_0000_1010   //019  01 08000a LDA  acc <- (8000a)  end testing the Flash Registers
0000_0000_0000_0000_0000_0000_0010_0001   //01a  00 000021 LDA  acc <- (21)     start testing the D-Cache Registers
0000_0001_0000_1000_0000_0000_0001_0000   //01b  01 080010 STO  (80010) <- acc
0000_0000_0000_0000_0000_0000_0010_0010   //01c  00 000022 LDA  acc <- (22)
0000_0001_0000_1000_0000_0000_0001_0001   //01d  01 080011 STO  (80011) <- acc
0000_0000_0000_0000_0000_0000_0010_0011   //01e  00 000023 LDA  acc <- (23)
0000_0001_0000_1000_0000_0000_0001_0010   //01f  01 080012 STO  (80012) <- acc
0000_0100_0000_0000_0000_0000_0010_0100   //020  04 000024 JMP  (024)
0000_0000_0000_0000_0000_0000_0001_0110   //021 Value is 16
0000_0000_0000_0000_0000_0000_0001_0111   //022 Value is 17
0000_0000_0000_0000_0000_0000_0001_1000   //023 Value is 18
0000_0000_0000_1000_0000_0000_0001_0000   //024  01 080010 LDA  acc <- (80010)
0000_0000_0000_1000_0000_0000_0001_0001   //025  01 080011 LDA  acc <- (80011)
0000_0000_0000_1000_0000_0000_0001_0010   //026  01 080012 LDA  acc <- (80012)  end testing the D-Cache Registers
0000_0000_0000_0000_0000_0000_0010_1110   //027  00 00002e LDA  acc <- (2e)     start testing the i-Cache Registers
0000_0001_0000_1000_0000_0000_0001_1001   //028  01 080019 STO  (80019) <- acc
0000_0000_0000_0000_0000_0000_0010_1111   //029  00 00002f LDA  acc <- (2f)
0000_0001_0000_1000_0000_0000_0001_1010   //02a  01 08001A STO  (8001A) <- acc
0000_0000_0000_0000_0000_0000_0011_0000   //02b  00 000030 LDA  acc <- (30)
0000_0001_0000_1000_0000_0000_0001_1011   //02c  01 08001B STO  (8001B) <- acc
0000_0100_0000_0000_0000_0000_0011_0001   //02d  04 000031 JMP  (031)
0000_0000_0000_0000_0000_0000_0001_1001   //02e Value is 19
0000_0000_0000_0000_0000_0000_0001_1010   //02f Value is 1A
0000_0000_0000_0000_0000_0000_0001_1011   //030 Value is 1B
0000_0000_0000_1000_0000_0000_0001_1001   //031  01 080019 LDA  acc <- (80019)
0000_0000_0000_1000_0000_0000_0001_1010   //032  01 08001A LDA  acc <- (8001A)
0000_0000_0000_1000_0000_0000_0001_1011   //033  01 08001B LDA  acc <- (8001B)  end testing the i-Cache Registers
0000_0000_0000_0000_0000_0000_0011_1001   //034  00 000039 LDA  acc <- (39)     start testing the Timer Registers
0000_0001_0000_1000_0000_0000_0010_0001   //035  01 080021 STO  (80021) <- acc
0000_0000_0000_0000_0000_0000_0011_1010   //036  00 00003a LDA  acc <- (3a)
0000_0001_0000_1000_0000_0000_0010_0010   //037  01 080022 STO  (80022) <- acc
0000_0100_0000_0000_0000_0000_0011_1011   //038  04 00003b JMP  (03b)
0000_0000_0000_0000_0000_0000_0001_1100   //039 Value is 1C
0000_0000_0000_0000_0000_0000_0001_1101   //03a Value is 1D
0000_0000_0000_1000_0000_0000_0010_0001   //03b  01 080021 LDA  acc <- (80021)
0000_0000_0000_1000_0000_0000_0010_0010   //03c  01 080022 LDA  acc <- (80022)  end testing the Timer Registers
0000_0000_0000_0000_0000_0000_0100_0010   //03d  00 000042 LDA  acc <- (42)     start testing the UART Registers
0000_0001_0000_1000_0000_0000_0010_1010   //03e  01 08002A STO  (8002A) <- acc
0000_0000_0000_0000_0000_0000_0100_0011   //03f  00 000043 LDA  acc <- (43)
0000_0001_0000_1000_0000_0000_0010_1011   //040  01 08002B STO  (8002B) <- acc
0000_0100_0000_0000_0000_0000_0100_0100   //041  04 000044 JMP  (044)
0000_0000_0000_0000_0000_0000_0001_1110   //042 Value is 1E
0000_0000_0000_0000_0000_0000_0001_1111   //043 Value is 1F
0000_0000_0000_1000_0000_0000_0010_1010   //044  01 08002A LDA  acc <- (8002A)
0000_0000_0000_1000_0000_0000_0010_1011   //045  01 08002B LDA  acc <- (8002B)  end testing the UART Registers
0000_0111_0000_0000_0000_0000_0000_0000   //046  07 000000 STP  STOP

/*********************************************************
 * This program developed by Hossein Amidi  (C) May 2002 *
 * It's the Machine Language with Assembly Comment on the*
 * side for users to trace each instructions back to the *
 * RISC CPU.                                             *
 * This CPU Architecture uses a 32-bit Instructions with *
 * 256 Opcode (2 ^ 8-bit) and 16MB code and data acce-   *
 * sibility ( 2 ^ 24-bit). Entire machine Code and data  *
 * will be stored in the memory space.                   *
 * All the internal Registers for :                      *
 * 1) DMA                                                *
 * 2) Data Cache                                         *
 * 3) Instruction Cache                                  *
 * 4) UART                                               *
 * 5) Timer                                              *
 * 6) Flash Controller                                   *
 * 7) SDRAM Controller                                   *
 * will be accessed using a memory map methodology.      *
 *                                                       *
 * This program will test internal register for all the  *
 * above mentioned device's internal registers by  doing *
 * individual write / read to memory map locations.      *
 *********************************************************/