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[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [esoc_ctrl_in.txt] - Rev 49

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--
-- Test R/W access through the control interface  to ESOC
--
-- access the ESOC CONTROL UNIT
--
mr 8000 00000000
mr 8001 00010000
mr 8002 00000008
mw 8000 32100123
mr 8000 32100123
wt 100
--
-- access the ESOC DATA BUS ARBITER UNIT
--
mr 8800 00000000
mw 8800 FED00DEF
mr 8800 FED00DEF
wt 100
--
-- access the ESOC PORT 0 UNIT
--
mr 0005 000005EE
mw 0005 00000432
mr 0005 00000432
wt 100
mr 0180 00000001
mw 0180 ABC00ABC
mr 0180 ABC00ABC
wt 100
--
-- access the ESOC PORT 7 UNIT
--
mr 3805 000005EE
mw 3805 00000100
mr 3805 00000100
wt 100
mr 3980 00000001
mw 3980 12300321
mr 3980 12300321
wt 100
--
-- check all written registers again
--
mr 8000 32100123
mr 8800 FED00DEF
mr 0005 00000432
mr 0180 ABC00ABC
mr 3805 00000100
mr 3980 12300321

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